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| author | Josh Blum <josh@joshknows.com> | 2012-02-01 09:47:07 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-01 09:47:07 -0800 |
| commit | c407516349601831767952a9b12a077a2f23ea51 (patch) | |
| tree | 5733a0bf569d354dad9890b0a2fc024856ad5df5 /usrp2 | |
| parent | 7b69532aca8cc44017dedc1bfb07fa0d27b8ea6d (diff) | |
| download | uhd-c407516349601831767952a9b12a077a2f23ea51.tar.gz uhd-c407516349601831767952a9b12a077a2f23ea51.tar.bz2 uhd-c407516349601831767952a9b12a077a2f23ea51.zip | |
dsp rework: paramaterize post_engine_buffering
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/N2x0/u2plus_core.v | 1 | ||||
| -rw-r--r-- | usrp2/top/USRP2/u2_core.v | 1 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 18 |
3 files changed, 16 insertions, 4 deletions
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v index 0ee66d170..f04d449be 100644 --- a/usrp2/top/N2x0/u2plus_core.v +++ b/usrp2/top/N2x0/u2plus_core.v @@ -661,6 +661,7 @@ module u2plus_core wire strobe_tx; vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), + .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v index 746853fbf..d29f31b8f 100644 --- a/usrp2/top/USRP2/u2_core.v +++ b/usrp2/top/USRP2/u2_core.v @@ -647,6 +647,7 @@ module u2_core wire strobe_tx; vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(DSP_TX_FIFOSIZE), + .POST_ENGINE_FIFOSIZE(DSP_TX_FIFOSIZE+1), .REPORT_ERROR(1), .DO_FLOW_CONTROL(1), .PROT_ENG_FLAGS(1), .USE_TRANS_HEADER(1), .DSP_NUMBER(0)) diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 189876015..61df19097 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -19,6 +19,7 @@ module vita_tx_chain #(parameter BASE=0, parameter FIFOSIZE=10, + parameter POST_ENGINE_FIFOSIZE=0, parameter REPORT_ERROR=0, parameter DO_FLOW_CONTROL=0, parameter PROT_ENG_FLAGS=0, @@ -83,10 +84,19 @@ module vita_tx_chain .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); - fifo_cascade #(.WIDTH(36), .SIZE(9)) post_engine_buffering( - .clk(clk), .reset(reset), .clear(clear), - .datain(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1), - .dataout(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2)); + generate + if (POST_ENGINE_FIFOSIZE==0) begin + assign tx_data_int2 = tx_data_int1; + assign tx_src_rdy_int2 = tx_src_rdy_int1; + assign tx_dst_rdy_int1 = tx_dst_rdy_int2; + end + else begin + fifo_cascade #(.WIDTH(36), .SIZE(POST_ENGINE_FIFOSIZE)) post_engine_buffering( + .clk(clk), .reset(reset), .clear(clear), + .datain(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1), + .dataout(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2)); + end + endgenerate vita_tx_deframer #(.BASE(BASE), .MAXCHAN(MAXCHAN), |