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| author | Matt Ettus <matt@ettus.com> | 2011-10-26 15:10:57 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-10-26 15:57:22 -0700 |
| commit | 52c2287981f622a9e01aaed3028fd32d33b5be59 (patch) | |
| tree | 27167f2427bf1a86cdd64c3104b73cf4e585826f /usrp2 | |
| parent | e1889d5e86b48156904b5f295644ed417064890f (diff) | |
| download | uhd-52c2287981f622a9e01aaed3028fd32d33b5be59.tar.gz uhd-52c2287981f622a9e01aaed3028fd32d33b5be59.tar.bz2 uhd-52c2287981f622a9e01aaed3028fd32d33b5be59.zip | |
u1e/u1p: remove unused UART
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/B100/u1plus_core.v | 13 | ||||
| -rw-r--r-- | usrp2/top/E1x0/u1e_core.v | 11 |
2 files changed, 0 insertions, 24 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index e11a4c37e..461b4c199 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -354,19 +354,6 @@ module u1plus_core assign s0_ack = s0_stb & s0_cyc; // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 1, UART - // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock - -/* - simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), - .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), - .rx_int_o(),.tx_int_o(), - .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); -*/ - - // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI spi_top16 shared_spi diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v index adc3c5aab..025df3065 100644 --- a/usrp2/top/E1x0/u1e_core.v +++ b/usrp2/top/E1x0/u1e_core.v @@ -348,17 +348,6 @@ module u1e_core assign s0_ack = s0_stb & s0_cyc; // ///////////////////////////////////////////////////////////////////////////////////// - // Slave 1, UART - // depth of 3 is 128 entries, clkdiv of 278 gives 230.4k with a 64 MHz system clock - - simple_uart #(.TXDEPTH(3),.RXDEPTH(3), .CLKDIV_DEFAULT(278)) uart - (.clk_i(wb_clk),.rst_i(wb_rst), - .we_i(s1_we),.stb_i(s1_stb),.cyc_i(s1_cyc),.ack_o(s1_ack), - .adr_i(s1_adr[3:1]),.dat_i({16'd0,s1_dat_mosi}),.dat_o(s1_dat_miso), - .rx_int_o(),.tx_int_o(), - .tx_o(debug_txd),.rx_i(debug_rxd),.baud_o()); - - // ///////////////////////////////////////////////////////////////////////////////////// // Slave 2, SPI spi_top16 shared_spi |