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| author | Matt Ettus <matt@ettus.com> | 2010-07-19 15:08:30 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-19 15:08:30 -0700 |
| commit | 33083078546a910268ee404fc592c7df31451ebc (patch) | |
| tree | 1e65d38576a626cfc8c04c499ad0a1b2b71e215b /usrp2 | |
| parent | 5cd32136a24138de33020bb91d38efd8d6517773 (diff) | |
| download | uhd-33083078546a910268ee404fc592c7df31451ebc.tar.gz uhd-33083078546a910268ee404fc592c7df31451ebc.tar.bz2 uhd-33083078546a910268ee404fc592c7df31451ebc.zip | |
move declaration ahead of use
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core_udp.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v index a074f099e..b034791a7 100644 --- a/usrp2/top/u2_rev3/u2_core_udp.v +++ b/usrp2/top/u2_rev3/u2_core_udp.v @@ -180,6 +180,11 @@ module u2_core wire [31:0] irq; wire [63:0] vita_time; + wire run_rx, run_tx; + reg run_rx_d1; + always @(posedge dsp_clk) + run_rx_d1 <= run_rx; + // /////////////////////////////////////////////////////////////////////////////////////////////// // Wishbone Single Master INTERCON localparam dw = 32; // Data bus width @@ -566,11 +571,6 @@ module u2_core // ///////////////////////////////////////////////////////////////////////// // ATR Controller, Slave #11 - wire run_rx, run_tx; - reg run_rx_d1; - always @(posedge dsp_clk) - run_rx_d1 <= run_rx; - atr_controller atr_controller (.clk_i(wb_clk),.rst_i(wb_rst), .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i), |