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| author | Matt Ettus <matt@ettus.com> | 2010-11-07 14:32:01 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 18:57:38 -0800 |
| commit | a78ace9e161a0fc30a6cc6de38b9eea45230a4b6 (patch) | |
| tree | e57594e63feae7d6d186c1616a51475edbc2c2d7 /usrp2 | |
| parent | ae0d02442ab892e9800b127d6ba1eed70716bb99 (diff) | |
| download | uhd-a78ace9e161a0fc30a6cc6de38b9eea45230a4b6.tar.gz uhd-a78ace9e161a0fc30a6cc6de38b9eea45230a4b6.tar.bz2 uhd-a78ace9e161a0fc30a6cc6de38b9eea45230a4b6.zip | |
compiles with new file locations
Diffstat (limited to 'usrp2')
| -rwxr-xr-x | usrp2/vrt/vita_tx.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_tx.build b/usrp2/vrt/vita_tx.build index 902929c08..e7106aa10 100755 --- a/usrp2/vrt/vita_tx.build +++ b/usrp2/vrt/vita_tx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v +iverilog -Wimplict -Wportbind -y ../sdr_lib -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_tx_tb vita_tx_tb.v |