Merge branch 'master' into next

* master:
  u2p: N200 Makefile
  u1e: use icarus verilog for lint
  clean up a bunch of warnings and incorrect bus widths

10 files changed, 120 insertions, 34 deletions

diff --git a/usrp2/control_lib/atr_controller.v b/usrp2/control_lib/atr_controller.v
index fed2791f9..a161b5e00 100644
--- a/usrp2/control_lib/atr_controller.v
+++ b/usrp2/control_lib/atr_controller.v
@@ -7,7 +7,7 @@ module atr_controller
   (input clk_i, input rst_i,
    input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o,
    input we_i, input stb_i, input cyc_i, output reg ack_o,
-   input run_rx, input run_tx, input [31:0] master_time,
+   input run_rx, input run_tx,
    output [31:0] ctrl_lines);
    
    reg [3:0] state;
diff --git a/usrp2/control_lib/atr_controller16.v b/usrp2/control_lib/atr_controller16.v
index 3d8b5b1e9..74ce30a54 100644
--- a/usrp2/control_lib/atr_controller16.v
+++ b/usrp2/control_lib/atr_controller16.v
@@ -7,7 +7,7 @@ module atr_controller16
   (input clk_i, input rst_i,
    input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o,
    input we_i, input stb_i, input cyc_i, output reg ack_o,
-   input run_rx, input run_tx, input [31:0] master_time,
+   input run_rx, input run_tx,
    output [31:0] ctrl_lines);
    
    reg [3:0] state;
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index 1318809d6..a315234cf 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -7,8 +7,6 @@ module dsp_core_rx
    input [13:0] adc_a, input adc_ovf_a,
    input [13:0] adc_b, input adc_ovf_b,
    
-   input [15:0] io_rx,
-
    output [31:0] sample,
    input run,
    output strobe,
@@ -33,10 +31,6 @@ module dsp_core_rx
    wire        enable_hb1, enable_hb2;
    wire [7:0]  cic_decim_rate;
 
-   wire [31:10] UNUSED_1;
-   wire [31:4] 	UNUSED_2;
-   wire [31:2] 	UNUSED_3;
-   
    setting_reg #(.my_addr(BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
@@ -45,9 +39,9 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({scale_i,scale_q}),.changed());
    
-   setting_reg #(.my_addr(BASE+2)) sr_2
+   setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+      .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
    rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
      (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -60,12 +54,12 @@ module dsp_core_rx
    wire [7:0]  muxctrl;
    setting_reg #(.my_addr(BASE+5), .width(8)) sr_8
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out({UNUSED_2,muxctrl}),.changed());
+      .in(set_data),.out(muxctrl),.changed());
 
    wire [1:0] gpio_ena;
    setting_reg #(.my_addr(BASE+6), .width(2)) sr_9
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
+      .in(set_data),.out(gpio_ena),.changed());
 
    always @(posedge clk)
      case(muxctrl[3:0])		// The I mapping
@@ -153,19 +147,9 @@ module dsp_core_rx
    round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
    round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
 
-   // Streaming GPIO
-   //
-   // io_rx[15] => I channel LSB if gpio_ena[0] high
-   // io_rx[14] => Q channel LSB if gpio_ena[1] high
-
    reg [31:0] sample_reg;
    always @(posedge clk)
-     begin
-	sample_reg[31:17] <= i_out[15:1];
-	sample_reg[15:1]  <= q_out[15:1];
-	sample_reg[16]    <= gpio_ena[0] ? io_rx[15] : i_out[0]; 
-	sample_reg[0]     <= gpio_ena[1] ? io_rx[14] : q_out[0];
-     end
+     sample_reg <= {i_out,q_out};
    
    assign      sample = sample_reg;
    assign      strobe = strobe_hb2;
diff --git a/usrp2/top/u1e/core_compile b/usrp2/top/u1e/core_compile
new file mode 100755
index 000000000..fb1b2a854
--- /dev/null
+++ b/usrp2/top/u1e/core_compile
@@ -0,0 +1,2 @@
+iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v  2>&1  
+
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index b3d71b4ab..1e3b08465 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -11,7 +11,7 @@ module u1e_core
    input EM_NWE, input EM_NOE,
    
    inout db_sda, inout db_scl,
-   output sclk, output [7:0] sen, output mosi, input miso,
+   output sclk, output [15:0] sen, output mosi, input miso,
 
    input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
    output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
@@ -127,7 +127,7 @@ module u1e_core
    wire [31:0] 	 sample_rx, sample_tx;
    wire 	 strobe_rx, strobe_tx;
    wire 	 rx1_dst_rdy, rx1_src_rdy;
-   wire [99:0] 	 rx1_data;
+   wire [100:0]  rx1_data;
    wire 	 run_rx;
    wire [35:0] 	 vita_rx_data;
    wire 	 vita_rx_src_rdy, vita_rx_dst_rdy;
@@ -368,7 +368,7 @@ module u1e_core
 
    atr_controller16 atr_controller16
      (.clk_i(wb_clk), .rst_i(wb_rst),
-      .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
+      .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso),
       .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack),
       .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines));
 
@@ -383,7 +383,7 @@ module u1e_core
 
    wb_readback_mux_16LE readback_mux_32
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb),
-      .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack),
+      .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack),
 
       .word00(vita_time[63:32]),        .word01(vita_time[31:0]),
       .word02(vita_time_pps[63:32]),    .word03(vita_time_pps[31:0]),
@@ -400,7 +400,8 @@ module u1e_core
 
    time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit
      (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int));
+      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
+      .exp_time_in(0));
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
diff --git a/usrp2/top/u2plus/Makefile.N200 b/usrp2/top/u2plus/Makefile.N200
new file mode 100644
index 000000000..9175f9304
--- /dev/null
+++ b/usrp2/top/u2plus/Makefile.N200
@@ -0,0 +1,98 @@
+#
+# Copyright 2008 Ettus Research LLC
+#
+
+##################################################
+# Project Setup
+##################################################
+TOP_MODULE = u2plus
+BUILD_DIR = $(abspath build$(ISE)-N200)
+
+##################################################
+# Include other makefiles
+##################################################
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd1800a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+TOP_SRCS = \
+u2plus_core.v \
+u2plus.v \
+u2plus.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
+
+##################################################
+# Process Properties
+##################################################
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+TRANSLATE_PROPERTIES = \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+MAP_PROPERTIES = \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+PLACE_ROUTE_PROPERTIES = \
+"Place & Route Effort Level (Overall)" High 
+
+STATIC_TIMING_PROPERTIES = \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+GEN_PROG_FILE_PROPERTIES = \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/vrt/trigger_context_pkt.v b/usrp2/vrt/trigger_context_pkt.v
index 226ec45f2..1d456814b 100644
--- a/usrp2/vrt/trigger_context_pkt.v
+++ b/usrp2/vrt/trigger_context_pkt.v
@@ -10,7 +10,7 @@ module trigger_context_pkt
    wire [15:0] packets;
    wire [6:0]  dummy1;
    wire [14:0] dummy2;
-   wire        enable_timed, enable_consumed;
+   wire        enable_cycle, enable_consumed;
    reg [30:0]  cycle_count, packet_count;
 
    
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 6f567668d..fa84d7a2f 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -27,16 +27,17 @@ module vita_tx_chain
    wire 		trigger, sent;
    wire [31:0] 		debug_vtc, debug_vtd, debug_tx_dsp;
 
-   wire 		error, packet_consumed;
+   wire 		error, packet_consumed, ack;
    wire [31:0] 		error_code;
    wire 		clear_seqnum;
    wire [31:0] 		current_seqnum;
+   wire 		strobe_tx;
    
    assign underrun = error;
    assign message = error_code;
    
    setting_reg #(.my_addr(BASE_CTRL+1)) sr
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(clear_vita));
 
    setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index e966d987c..14b97a215 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -71,7 +71,7 @@ module vita_tx_control
 
    wire [31:0] error_policy;
    setting_reg #(.my_addr(BASE+3)) sr_error_policy
-     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(error_policy),.changed());
 
    wire        policy_wait = error_policy[0];
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index eb39feaec..163c2af20 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -38,8 +38,8 @@ module vita_tx_deframer
    assign has_secs 	= ~(data_i[23:22]==2'b00);
    assign has_tics 	= ~(data_i[21:20]==2'b00);
    assign has_trailer 	= data_i[26];
-   assign is_sob = data_i[25];
-   assign is_eob = data_i[24];
+   wire      is_sob = data_i[25];
+   wire      is_eob = data_i[24];
    wire      eof = data_i[33];
    reg 	     has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg;
    reg 	     has_trailer_reg, is_sob_reg, is_eob_reg;