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| author | Josh Blum <josh@joshknows.com> | 2012-01-30 15:09:47 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-01-30 15:09:47 -0800 |
| commit | 05644d7d4fe2df455b01833cc0fc8aa1b4b6e1f3 (patch) | |
| tree | 49f2ce0d9eda6652099acf6d1bea24a58448006e /usrp2 | |
| parent | ac35b413a595617c1fa57766758c06ccfe3f320e (diff) | |
| download | uhd-05644d7d4fe2df455b01833cc0fc8aa1b4b6e1f3.tar.gz uhd-05644d7d4fe2df455b01833cc0fc8aa1b4b6e1f3.tar.bz2 uhd-05644d7d4fe2df455b01833cc0fc8aa1b4b6e1f3.zip | |
dsp rework: integrated dspengine_8to16, some tweaks
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/sdr_lib/Makefile.srcs | 3 | ||||
| -rw-r--r-- | usrp2/sdr_lib/dspengine_8to16.v | 7 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs index 0f1958991..840627e6d 100644 --- a/usrp2/sdr_lib/Makefile.srcs +++ b/usrp2/sdr_lib/Makefile.srcs @@ -1,5 +1,5 @@ # -# Copyright 2010 Ettus Research LLC +# Copyright 2010-2012 Ettus Research LLC # ################################################## @@ -26,6 +26,7 @@ cordic_stage.v \ ddc_chain.v \ duc_chain.v \ dspengine_16to8.v \ +dspengine_8to16.v \ hb_dec.v \ hb_interp.v \ pipectrl.v \ diff --git a/usrp2/sdr_lib/dspengine_8to16.v b/usrp2/sdr_lib/dspengine_8to16.v index 39cf440f6..a0d2f7e7e 100644 --- a/usrp2/sdr_lib/dspengine_8to16.v +++ b/usrp2/sdr_lib/dspengine_8to16.v @@ -1,5 +1,5 @@ -// Copyright 2011 Ettus Research LLC +// Copyright 2012 Ettus Research LLC // // This program is free software: you can redistribute it and/or modify // it under the terms of the GNU General Public License as published by @@ -71,6 +71,7 @@ module dspengine_8to16 reg [15:0] length; reg wait_for_trailer; reg [15:0] data_in_len, data_out_len; + wire [15:0] data_in_lenx2 = {data_in_len[14:0], 1'b0} - (access_dat_i[20] & access_dat_i[8]); reg [7:0] i8_0, q8_0; wire [7:0] i8_1 = access_dat_i[15:8]; @@ -123,8 +124,8 @@ module dspengine_8to16 dsp_state <= DSP_WRITE_TRAILER; new_trailer <= access_dat_i[31:0]; // Leave trailer unchanged odd <= access_dat_i[20] & access_dat_i[8]; - data_out_len <= {data_in_len,1'b0} - (access_dat_i[20] & access_dat_i[8]); - write_adr <= hdr_length_reg + {data_in_len,1'b0} - (access_dat_i[20] & access_dat_i[8]); + data_out_len <= data_in_lenx2; + write_adr <= hdr_length_reg + data_in_lenx2; end DSP_WRITE_TRAILER : diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 7ea3978af..f9348bbfd 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -75,15 +75,13 @@ module vita_tx_chain .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .data_o(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2)); -/* - dspengine_8to16 #(.BASE(BASE+X), .BUF_SIZE(FIFOSIZE)) dspengine_16to8 + + dspengine_8to16 #(.BASE(BASE+6), .BUF_SIZE(FIFOSIZE)) dspengine_8to16 (.clk(clk),.reset(reset),.clear(clear), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); -*/ - assign access_done = access_ok; //passthrough vita_tx_deframer #(.BASE(BASE), .MAXCHAN(MAXCHAN), |