dspengine: insert into the rx chain

4 files changed, 29 insertions, 2 deletions

diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index a1c11c026..a88f156c5 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -11,7 +11,9 @@ atr_controller.v \
 bin2gray.v \
 dcache.v \
 decoder_3_8.v \
+dbsm.v \
 dpram32.v \
+double_buffer.v \
 gray2bin.v \
 gray_send.v \
 icache.v \
diff --git a/usrp2/control_lib/double_buffer.v b/usrp2/control_lib/double_buffer.v
index eabd0f956..e8e565963 100644
--- a/usrp2/control_lib/double_buffer.v
+++ b/usrp2/control_lib/double_buffer.v
@@ -54,7 +54,7 @@ module double_buffer
    assign rw0_adr = (read_ok & ~read_ptr) ? read_adr : write_adr;
    assign rw1_adr = (read_ok & read_ptr) ? read_adr : write_adr;
    
-   wire [35:0] 	       access_dat_i, access_dat_o_0, access_dat_o_1;
+   wire [35:0] 	       access_dat_o_0, access_dat_o_1;
    wire 	       access_ptr;
    assign access_dat_o = access_ptr? access_dat_o_1 : access_dat_o_0;
    
diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs
index defbced17..629b92cc8 100644
--- a/usrp2/sdr_lib/Makefile.srcs
+++ b/usrp2/sdr_lib/Makefile.srcs
@@ -25,8 +25,11 @@ cordic_z24.v \
 cordic_stage.v \
 dsp_core_rx.v \
 dsp_core_tx.v \
+dspengine_16to8.v \
 hb_dec.v \
 hb_interp.v \
+pipectrl.v \
+pipestage.v \
 round.v \
 round_reg.v \
 round_sd.v \
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index 1986743b3..28b5ea9ff 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -50,11 +50,33 @@ module vita_rx_chain
       .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int),
       .debug_rx(vrf_debug) );
 
+   wire [FIFOSIZE-1:0] access_adr, access_len;
+   wire 	       access_we, access_stb, access_ok, access_done, access_skip_read;
+   wire [35:0] 	       dsp_to_buf, buf_to_dsp;
+   wire [35:0] 	       rx_data_int2;
+   wire 	       rx_src_rdy_int2, rx_dst_rdy_int2;
+   
+   double_buffer #(.BUF_SIZE(FIFOSIZE)) db
+     (.clk(clk),.reset(reset),.clear(clear),
+      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+      .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),
+
+      .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int),
+      .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2));
+
+   dspengine_16to8 #(.BASE(BASE+3), .BUF_SIZE(FIFOSIZE)) dspengine_16to8
+     (.clk(clk),.reset(rst),.clear(clear),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
+      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
+      .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
+   
    dsp_framer36 #(.BUF_SIZE(FIFOSIZE), 
 		  .PORT_SEL(UNIT), 
 		  .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp0_framer36
      (.clk(clk), .reset(reset), .clear(clear),
-      .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int),
+      .data_i(rx_data_int2), .src_rdy_i(rx_src_rdy_int2), .dst_rdy_o(rx_dst_rdy_int2),
       .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) );
 
    assign debug = vrc_debug; //  | vrf_debug;