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| author | Matt Ettus <matt@ettus.com> | 2010-10-01 15:18:26 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-09 18:56:31 -0800 |
| commit | 76d2697276c067285135f444112d987ee53cb843 (patch) | |
| tree | 65c82505120d30666d82819db73c86a11d19a4c7 /usrp2 | |
| parent | 0edd06b736fb55cc740c5cf1cbe1ba718b8f3ef0 (diff) | |
| download | uhd-76d2697276c067285135f444112d987ee53cb843.tar.gz uhd-76d2697276c067285135f444112d987ee53cb843.tar.bz2 uhd-76d2697276c067285135f444112d987ee53cb843.zip | |
fix timing problem on DAC output bus
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index 4daa66212..bab5a7706 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -330,8 +330,8 @@ module u2_rev3 wire [15:0] dac_a_int, dac_b_int; // DAC A and B are swapped in schematic to facilitate clean layout // DAC A is also inverted in schematic to facilitate clean layout - always @(negedge dsp_clk) dac_a <= ~dac_b_int; - always @(negedge dsp_clk) dac_b <= dac_a_int; + always @(posedge dsp_clk) dac_a <= ~dac_b_int; + always @(posedge dsp_clk) dac_b <= dac_a_int; /* OFDDRRSE OFDDRRSE_serdes_inst |