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| author | Matt Ettus <matt@ettus.com> | 2010-05-17 20:59:55 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-17 20:59:55 -0700 |
| commit | 47230fadfbbde3b45fbf57e8ff506f4fac812ca2 (patch) | |
| tree | 7ddb0f46085a431d4f59fc1dde55ddcdf0b45e2e /usrp2 | |
| parent | b04a1beaab300000ce2d8a5814bd2e37af48286c (diff) | |
| download | uhd-47230fadfbbde3b45fbf57e8ff506f4fac812ca2.tar.gz uhd-47230fadfbbde3b45fbf57e8ff506f4fac812ca2.tar.bz2 uhd-47230fadfbbde3b45fbf57e8ff506f4fac812ca2.zip | |
better debug pins
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u1e/u1e_core.v | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v index 903121832..4637df0cc 100644 --- a/usrp2/top/u1e/u1e_core.v +++ b/usrp2/top/u1e/u1e_core.v @@ -1,8 +1,8 @@ -//`define LOOPBACK 1 +`define LOOPBACK 1 //`define TIMED 1 -`define CRC 1 +//`define CRC 1 module u1e_core (input clk_fpga, input rst_fpga, @@ -372,12 +372,10 @@ module u1e_core // Debug circuitry assign debug_clk = { EM_CLK, clk_fpga }; -/* - assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, + assign debug = { { rx_have_data, tx_have_space, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] }, { EM_D } }; -*/ - assign debug = { phase[23:8], txsync, txblank, tx }; + //assign debug = { phase[23:8], txsync, txblank, tx }; assign debug_gpio_0 = { debug_gpmc }; |