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| author | Josh Blum <josh@joshknows.com> | 2011-07-28 00:35:31 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-28 00:53:35 -0700 |
| commit | 0b7fe5b3d1e7ad4e72e8a894238174d927030498 (patch) | |
| tree | 177a9435f3d3f37cff33368aefe750e474ca028b /usrp2 | |
| parent | 64cf011b0845ad553ec8bfb91fabd903bd7c14fc (diff) | |
| download | uhd-0b7fe5b3d1e7ad4e72e8a894238174d927030498.tar.gz uhd-0b7fe5b3d1e7ad4e72e8a894238174d927030498.tar.bz2 uhd-0b7fe5b3d1e7ad4e72e8a894238174d927030498.zip | |
vita_rx_ctrl: use an extra cmd bit to signal stop
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/vrt/vita_rx_control.v | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 39f32d7fe..b6b55d9d0 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -46,13 +46,13 @@ module vita_rx_control wire [63:0] rcvtime_pre; reg [63:0] rcvtime; - wire [28:0] numlines_pre; - wire send_imm_pre, chain_pre, reload_pre; + wire [27:0] numlines_pre; + wire send_imm_pre, chain_pre, reload_pre, stop_pre; reg send_imm, chain, reload; wire read_ctrl, not_empty_ctrl, write_ctrl; reg sc_pre2; wire [33:0] fifo_line; - reg [28:0] lines_left, lines_total; + reg [27:0] lines_left, lines_total; reg [2:0] ibs_state; wire now, early, late; wire sample_fifo_in_rdy; @@ -83,7 +83,7 @@ module vita_rx_control fifo_short #(.WIDTH(96)) commandfifo (.clk(clk),.reset(reset),.clear(clear), .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(), - .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), + .dataout({send_imm_pre,chain_pre,reload_pre,stop_pre,numlines_pre,rcvtime_pre}), .src_rdy_o(not_empty_ctrl), .dst_rdy_i(read_ctrl), .occupied(command_queue_len), .space() ); @@ -97,7 +97,7 @@ module vita_rx_control localparam IBS_LATECMD = 6; localparam IBS_ZEROLEN = 7; - wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & (numlines_pre==0))); + wire signal_cmd_done = (lines_left == 1) & (~chain | (not_empty_ctrl & stop_pre)); wire signal_overrun = (ibs_state == IBS_OVERRUN); wire signal_brokenchain = (ibs_state == IBS_BROKENCHAIN); wire signal_latecmd = (ibs_state == IBS_LATECMD); @@ -144,7 +144,7 @@ module vita_rx_control lines_left <= numlines_pre; lines_total <= numlines_pre; rcvtime <= rcvtime_pre; - if(numlines_pre == 0) + if(stop_pre) ibs_state <= IBS_ZEROLEN; else ibs_state <= IBS_WAITING; @@ -182,7 +182,7 @@ module vita_rx_control send_imm <= send_imm_pre; chain <= chain_pre; reload <= reload_pre; - if(numlines_pre == 0) // If we are told to stop here + if(stop_pre) // If we are told to stop here ibs_state <= IBS_IDLE; else ibs_state <= IBS_RUNNING; |