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authorMatt Ettus <matt@ettus.com>2010-04-15 16:14:24 -0700
committerMatt Ettus <matt@ettus.com>2010-04-15 16:14:24 -0700
commit883c60cad6756042b5e90785668be3dd98e920bf (patch)
tree5029d7c8b9f9d614c3bad78eb1fc83a53f30461a /usrp2
parent8f6ddf93ef81deb73a8b84496e115be299769951 (diff)
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add bus error reporting
Diffstat (limited to 'usrp2')
-rw-r--r--usrp2/gpmc/gpmc_to_fifo_async.v12
1 files changed, 9 insertions, 3 deletions
diff --git a/usrp2/gpmc/gpmc_to_fifo_async.v b/usrp2/gpmc/gpmc_to_fifo_async.v
index a8068022f..1df93f910 100644
--- a/usrp2/gpmc/gpmc_to_fifo_async.v
+++ b/usrp2/gpmc/gpmc_to_fifo_async.v
@@ -1,12 +1,12 @@
module gpmc_to_fifo_async
- (input [15:0] EM_D, input [1:0] EM_NBE,
- input EM_NCS, input EM_NWE,
+ (input [15:0] EM_D, input [1:0] EM_NBE, input EM_NCS, input EM_NWE,
input fifo_clk, input fifo_rst,
output reg [17:0] data_o, output reg src_rdy_o, input dst_rdy_i,
- input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready);
+ input [15:0] frame_len, input [15:0] fifo_space, output fifo_ready,
+ output reg bus_error );
reg [10:0] counter;
// Synchronize the async control signals
@@ -54,5 +54,11 @@ module gpmc_to_fifo_async
counter <= counter + 1;
assign fifo_ready = first_write & (fifo_space > frame_len);
+
+ always @(posedge fifo_clk)
+ if(fifo_rst)
+ bus_error <= 0;
+ else if(src_rdy_o & ~dst_rdy_i)
+ bus_error <= 1;
endmodule // gpmc_to_fifo_async