added DAC output pins, and a sine wave generator to test them

3 files changed, 63 insertions, 18 deletions

diff --git a/usrp2/top/u1e/u1e.ucf b/usrp2/top/u1e/u1e.ucf
index 055a1ef17..a73ebceb8 100644
--- a/usrp2/top/u1e/u1e.ucf
+++ b/usrp2/top/u1e/u1e.ucf
@@ -191,22 +191,22 @@ NET "dip_sw<0>"  LOC = "J7"  ;
 #NET "DA<1>"  LOC = "P22"  ;
 #NET "DA<0>"  LOC = "N17"  ;
 
-#NET "TX<13>"  LOC = "P19"  ;
-#NET "TX<12>"  LOC = "R18"  ;
-#NET "TX<11>"  LOC = "U20"  ;
-#NET "TX<10>"  LOC = "T20"  ;
-#NET "TX<9>"  LOC = "R19"  ;
-#NET "TX<8>"  LOC = "R20"  ;
-#NET "TX<7>"  LOC = "W22"  ;
-#NET "TX<6>"  LOC = "Y22"  ;
-#NET "TX<5>"  LOC = "T18"  ;
-#NET "TX<4>"  LOC = "T17"  ;
-#NET "TX<3>"  LOC = "W19"  ;
-#NET "TX<2>"  LOC = "V20"  ;
-#NET "TX<1>"  LOC = "Y21"  ;
-#NET "TX<0>"  LOC = "AA22"  ;
-#NET "TXSYNC"  LOC = "U18"  ;
-#NET "TXBLANK"  LOC = "U19"  ;
+NET "TX<13>"  LOC = "P19"  ;
+NET "TX<12>"  LOC = "R18"  ;
+NET "TX<11>"  LOC = "U20"  ;
+NET "TX<10>"  LOC = "T20"  ;
+NET "TX<9>"  LOC = "R19"  ;
+NET "TX<8>"  LOC = "R20"  ;
+NET "TX<7>"  LOC = "W22"  ;
+NET "TX<6>"  LOC = "Y22"  ;
+NET "TX<5>"  LOC = "T18"  ;
+NET "TX<4>"  LOC = "T17"  ;
+NET "TX<3>"  LOC = "W19"  ;
+NET "TX<2>"  LOC = "V20"  ;
+NET "TX<1>"  LOC = "Y21"  ;
+NET "TX<0>"  LOC = "AA22"  ;
+NET "TXSYNC"  LOC = "U18"  ;
+NET "TXBLANK"  LOC = "U19"  ;
 
 NET "PPS_IN"  LOC = "M17"  ;
 
diff --git a/usrp2/top/u1e/u1e.v b/usrp2/top/u1e/u1e.v
index 2ed6b71c8..35818e8c8 100644
--- a/usrp2/top/u1e/u1e.v
+++ b/usrp2/top/u1e/u1e.v
@@ -25,6 +25,9 @@ module u1e
    input overo_gpio128, input overo_gpio163, input overo_gpio170, input overo_gpio176, // Misc GPIO
    
    inout [15:0] io_tx, inout [15:0] io_rx,
+
+   output [13:0] TX, output TXSYNC, output TXBLANK,
+   
    input PPS_IN
    );
 
@@ -56,6 +59,7 @@ module u1e
 		     .tx_have_space(overo_gpio144), .tx_underrun(overo_gpio145),
 		     .rx_have_data(overo_gpio146), .rx_overrun(overo_gpio147),
 		     .io_tx(io_tx), .io_rx(io_rx),
+		     .tx(TX), .txsync(TXSYNC), .txblank(TXBLANK),
 		     .misc_gpio( {{overo_gpio128,overo_gpio163,overo_gpio170,overo_gpio176},
 				  {overo_gpio0,overo_gpio14,overo_gpio21,overo_gpio22},
 				  {overo_gpio23,overo_gpio64,overo_gpio65,overo_gpio127}}),
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index d5a3ddf68..74ffc4657 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -13,7 +13,10 @@ module u1e_core
 
    input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
    output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun,
-   inout [15:0] io_tx, inout [15:0] io_rx, input [11:0] misc_gpio, input pps_in
+   inout [15:0] io_tx, inout [15:0] io_rx, 
+   output reg [13:0] tx, output reg txsync, output txblank,
+   
+   input [11:0] misc_gpio, input pps_in
    );
    
    wire 	wb_clk = clk_fpga;
@@ -213,7 +216,7 @@ module u1e_core
    
    assign { debug_led[2],debug_led[0],debug_led[1] } = reg_leds;  // LEDs are arranged funny on board
    assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
-   assign { rx_overrun, tx_underrun } = reg_test;
+   assign { rx_overrun, tx_underrun } = 0; // reg_test;
    
    assign s0_dat_miso = (s0_adr[6:0] == REG_LEDS) ? reg_leds : 
 			(s0_adr[6:0] == REG_SWITCHES) ? {5'b0,debug_pb[2:0],dip_sw[7:0]} :
@@ -309,6 +312,44 @@ module u1e_core
    time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit
      (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+
+   
+   // /////////////////////////////////////////////////////////////////////////
+   // TX
+
+   assign txblank = 0;
+
+   wire [23:0] 	freq = {reg_test,8'd0};
+   
+   reg [23:0] 	tx_q_hold;
+   wire [23:0] 	tx_i, tx_q;
+   
+   reg 		tx_stb;
+   always @(posedge wb_clk)
+     tx_stb <= ~tx_stb;
+      
+   always @(posedge wb_clk)
+     if(tx_stb)
+       tx <= tx_i[23:10];
+     else
+       tx <= tx_q_hold[23:10];
+
+   always @(posedge wb_clk)
+     if(tx_stb)
+       tx_q_hold <= tx_q;
+   
+   always @(posedge wb_clk)
+     txsync <= ~tx_stb;   // TX Sync low indicates first data item
+   // We invert here if we don't use inv_txsync in the 9862
+
+   reg [23:0] 	phase;
+   always @(posedge wb_clk)
+     if(tx_stb)
+       phase <= phase + freq;
+   
+   cordic_z24 #(.bitwidth(24)) tx_cordic
+     (.clock(wb_clk), .reset(wb_rst), .enable(1),
+      .xi(24'd15000), .yi(24'd0), .zi(phase), .xo(tx_i), .yo(tx_q), .zo());
    
    // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry