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| author | Matt Ettus <matt@ettus.com> | 2010-05-04 12:30:56 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-04 12:30:56 -0700 |
| commit | 031becd1f05f0fbcab6a4f2be353292cd667a88f (patch) | |
| tree | 33fd5a9c2580615e98baa6729671f07bdecac4e8 /usrp2 | |
| parent | b30cbe85e8537de6a94e481a57033b5e57a73e12 (diff) | |
| download | uhd-031becd1f05f0fbcab6a4f2be353292cd667a88f.tar.gz uhd-031becd1f05f0fbcab6a4f2be353292cd667a88f.tar.bz2 uhd-031becd1f05f0fbcab6a4f2be353292cd667a88f.zip | |
add timing constraints. Just have main clock signal at 64 MHz for now.
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u1e/Makefile | 1 | ||||
| -rw-r--r-- | usrp2/top/u1e/timing.ucf | 13 |
2 files changed, 14 insertions, 0 deletions
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile index 5f712b046..2aebb33f9 100644 --- a/usrp2/top/u1e/Makefile +++ b/usrp2/top/u1e/Makefile @@ -186,6 +186,7 @@ gpmc/fifo_watcher.v \ gpmc/gpmc_wb.v \ top/u1e/u1e_core.v \ top/u1e/u1e.ucf \ +top/u1e/timing.ucf \ top/u1e/u1e.v ################################################## diff --git a/usrp2/top/u1e/timing.ucf b/usrp2/top/u1e/timing.ucf new file mode 100644 index 000000000..8df28c9d3 --- /dev/null +++ b/usrp2/top/u1e/timing.ucf @@ -0,0 +1,13 @@ + +NET "CLK_FPGA_P" TNM_NET = "CLK_FPGA_P"; +TIMESPEC "TS_clk_fpga_p" = PERIOD "CLK_FPGA_P" 15625 ps HIGH 50 %; + + + + +#NET "adc_a<*>" TNM_NET = ADC_DATA_GRP; +#NET "adc_b<*>" TNM_NET = ADC_DATA_GRP; +#TIMEGRP "ADC_DATA_GRP" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; + +#NET "adc_a<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; +#NET "adc_b<*>" OFFSET = IN 1 ns VALID 5 ns BEFORE "clk_fpga_p" RISING; |