dsp: add2_and_clip_reg and round_sd now are now strobed to be compatible

with strobed (non-full rate) data

6 files changed, 46 insertions, 26 deletions

diff --git a/usrp2/sdr_lib/add2_and_clip_reg.v b/usrp2/sdr_lib/add2_and_clip_reg.v
index 7070f1cea..8073b3b54 100644
--- a/usrp2/sdr_lib/add2_and_clip_reg.v
+++ b/usrp2/sdr_lib/add2_and_clip_reg.v
@@ -5,7 +5,9 @@ module add2_and_clip_reg
      input rst,
      input [WIDTH-1:0] in1,
      input [WIDTH-1:0] in2,
-     output reg [WIDTH-1:0] sum);
+     input strobe_in,
+     output reg [WIDTH-1:0] sum,
+     output reg strobe_out);
 
    wire [WIDTH-1:0] sum_int;
    
@@ -14,7 +16,10 @@ module add2_and_clip_reg
    always @(posedge clk)
      if(rst)
        sum <= 0;
-     else
+     else if(strobe_in)
        sum <= sum_int;
+
+   always @(posedge clk)
+     strobe_out <= strobe_in;
    
 endmodule // add2_and_clip_reg
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index f17c2816f..6a12836f2 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -102,10 +102,12 @@ module dsp_core_rx
 	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
 	      .signal_in(q_cordic),.signal_out(q_cic));
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
-   reg 	       strobe_cic_d1;
-   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
+   wire        strobe_cic_d1;
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_icic (.clk(clk),. in(i_cic), .strobe_in(strobe_cic), .out(i_cic_scaled), .strobe_out(strobe_cic_d1));
+   
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_qcic (.clk(clk), .in(q_cic), .strobe_in(strobe_cic), .out(q_cic_scaled), .strobe_out());
    
    small_hb_dec #(.WIDTH(18)) small_hb_i
      (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
@@ -124,13 +126,13 @@ module dsp_core_rx
      (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
       .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
 
-   round_reg #(.bits_in(18),.bits_out(16)) round_iout (.clk(clk),.in(i_hb2),.out(i_out));
-   round_reg #(.bits_in(18),.bits_out(16)) round_qout (.clk(clk),.in(q_hb2),.out(q_out));
-   reg 	       strobe_out;
-   always @(posedge clk) strobe_out <= strobe_hb2;
+   round_sd #(.bits_in(18),.bits_out(16)) 
+   round_iout (.clk(clk), .in(i_hb2), .strobe_in(strobe_hb2), .out(i_out), .strobe_out(strobe));
+   
+   round_sd #(.bits_in(18),.bits_out(16)) 
+   round_qout (.clk(clk), .in(q_hb2), .strobe_in(strobe_hb2), .out(q_out), .strobe_out());
    
    assign      sample = {i_hb2,q_hb2};
-   assign      strobe = strobe_out;
    assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
    
 endmodule // dsp_core_rx
diff --git a/usrp2/sdr_lib/round_sd.v b/usrp2/sdr_lib/round_sd.v
index b77c1471b..aeeb3502f 100644
--- a/usrp2/sdr_lib/round_sd.v
+++ b/usrp2/sdr_lib/round_sd.v
@@ -4,7 +4,8 @@ module round_sd
   #(parameter WIDTH_IN=18,
     parameter WIDTH_OUT=16)
    (input clk, input reset,
-    input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out);
+    input [WIDTH_IN-1:0] in, input strobe_in,
+    output [WIDTH_OUT-1:0] out, output strobe_out);
 
    localparam ERR_WIDTH = WIDTH_IN - WIDTH_OUT + 1;
 
@@ -14,7 +15,7 @@ module round_sd
    sign_extend #(.bits_in(ERR_WIDTH),.bits_out(WIDTH_IN)) ext_err (.in(err), .out(err_ext));
    
    add2_and_clip_reg #(.WIDTH(WIDTH_IN)) add2_and_clip_reg
-     (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .sum(sum));
+     (.clk(clk), .rst(reset), .in1(in), .in2(err_ext), .strobe_in(strobe_in), .sum(sum), .strobe_out(strobe_out));
    
    round #(.bits_in(WIDTH_IN),.bits_out(WIDTH_OUT)) round_sum (.in(sum), .out(out), .err(err));
    
diff --git a/usrp2/sdr_lib/round_sd_tb.v b/usrp2/sdr_lib/round_sd_tb.v
index 80b3707dc..1e8e9a323 100644
--- a/usrp2/sdr_lib/round_sd_tb.v
+++ b/usrp2/sdr_lib/round_sd_tb.v
@@ -11,8 +11,8 @@ module round_sd_tb();
    initial $dumpfile("round_sd_tb.vcd");
    initial $dumpvars(0,round_sd_tb);
 
-   localparam WIDTH_IN = 14;
-   localparam WIDTH_OUT = 10;
+   localparam WIDTH_IN = 8;
+   localparam WIDTH_OUT = 5;
    
    reg [WIDTH_IN-1:0] adc_in, adc_in_del;
    wire [WIDTH_OUT-1:0] adc_out;
@@ -37,15 +37,22 @@ module round_sd_tb();
 	end	
    
    round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT)) 
-   round_sd(.clk(clk),.reset(rst), .in(adc_in),.out(adc_out));
+   round_sd(.clk(clk),.reset(rst), .in(adc_in), .strobe_in(1'b1), .out(adc_out), .strobe_out());
 
+   reg [5:0] counter = 0;
+   
    always @(posedge clk)
-     adc_in <= 14'h1FDF;
-     //adc_in <= $random % 4739;
-
+     counter <= counter+1;
+   
    always @(posedge clk)
      adc_in_del <= adc_in;
 
-   initial #10000 $finish;
+   always @(posedge clk)
+     if(rst)
+       adc_in <= 0;
+     else if(counter == 63)
+       adc_in <= adc_in + 1;
+   
+   initial #300000 $finish;
    
 endmodule // longfifo_tb
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v
index 97923b9bf..350579056 100644
--- a/usrp2/sdr_lib/rx_dcoffset.v
+++ b/usrp2/sdr_lib/rx_dcoffset.v
@@ -49,9 +49,9 @@ module rx_dcoffset
        integrator <= integrator +  {{(alpha_shift){out[WIDTH-1]}},out};
 
    round_sd #(.WIDTH_IN(int_width),.WIDTH_OUT(WIDTH)) round_sd
-     (.clk(clk), .reset(rst), .in(integrator), .out(quantized));
+     (.clk(clk), .reset(rst), .in(integrator), .strobe_in(1'b1), .out(quantized), strobe_out());
    
    add2_and_clip_reg #(.WIDTH(WIDTH)) add2_and_clip_reg
-     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .sum(out));
+     (.clk(clk), .rst(rst), .in1(in), .in2(-quantized), .strobe_in(1'b1), .sum(out), strobe_out());
 
 endmodule // rx_dcoffset
diff --git a/usrp2/sdr_lib/rx_frontend.v b/usrp2/sdr_lib/rx_frontend.v
index 0ad83f6c7..98f72509c 100644
--- a/usrp2/sdr_lib/rx_frontend.v
+++ b/usrp2/sdr_lib/rx_frontend.v
@@ -63,13 +63,18 @@ module rx_frontend
    
    add2_and_clip_reg #(.WIDTH(24)) add_clip_i
      (.clk(clk), .rst(rst), 
-      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .sum(i_final));
+      .in1({adc_i_ofs,6'd0}), .in2({{4{corr_i[35]}},corr_i[35:16]}), .strobe_in(1'b1), 
+      .sum(i_final), .strobe_out());
    
    add2_and_clip_reg #(.WIDTH(24)) add_clip_q
      (.clk(clk), .rst(rst), 
-      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .sum(q_final));
+      .in1({adc_q_ofs,6'd0}), .in2({{4{corr_q[35]}},corr_q[35:16]}), .strobe_in(1'b1),
+      .sum(q_final), .strobe_out());
 
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_i (.clk(clk), .reset(rst), .in(i_final), .out(i_out));
-   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) round_q (.clk(clk), .reset(rst), .in(q_final), .out(q_out));
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_i (.clk(clk), .reset(rst), .in(i_final), .strobe_in(1'b1), .out(i_out), .strobe_out());
+   
+   round_sd #(.WIDTH_IN(24),.WIDTH_OUT(18)) 
+   round_q (.clk(clk), .reset(rst), .in(q_final), .strobe_in(1'b1), .out(q_out), .strobe_out());
    
 endmodule // rx_frontend