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authorMatt Ettus <matt@ettus.com>2010-10-06 18:15:17 -0700
committerMatt Ettus <matt@ettus.com>2010-11-11 12:10:35 -0800
commit2261035e69c033b37d9fe784ef8d1150f39f0e47 (patch)
treeebd7855601660c2b911cfd446bc73a658d13a6d8 /usrp2
parent84b42223ce7d119ef89ffa4030c904c1b8efc243 (diff)
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reconnect GPIOs, remove debug pins, meets timing now
Diffstat (limited to 'usrp2')
-rw-r--r--usrp2/top/u2_rev3/u2_core_udp.v8
1 files changed, 3 insertions, 5 deletions
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index b5d0ed72f..067a75759 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -414,7 +414,7 @@ module u2_core
.cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
.dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
.atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
- .gpio(/* {io_tx,io_rx}*/ ) );
+ .gpio({io_tx,io_rx}) );
// /////////////////////////////////////////////////////////////////////////
// Buffer Pool Status -- Slave #5
@@ -715,11 +715,9 @@ module u2_core
// /////////////////////////////////////////////////////////////////////////////////////////
// Debug Pins
- assign debug_clk = {dsp_clk, clk_to_mac};
- assign debug = debug_extfifo;
+ assign debug_clk = 2'b00; // {dsp_clk, clk_to_mac};
+ assign debug = 32'd0; // debug_extfifo;
assign debug_gpio_0 = 32'd0;
assign debug_gpio_1 = 32'd0;
- assign {io_tx,io_rx} = debug_extfifo2;
-
endmodule // u2_core