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authorMatt Ettus <matt@ettus.com>2010-08-30 15:11:05 -0700
committerMatt Ettus <matt@ettus.com>2010-08-30 15:11:05 -0700
commitc3cd5ccbf38294a3dd4ae1e386ddefb2071f59b6 (patch)
tree1ac8940c1756455feea6ac5714ab5a4992cea14c /usrp2
parent94e9baee9598f304b0e6918894876b16ffc8b2d7 (diff)
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add register to tell host about compatibility level and which image we are using
Diffstat (limited to 'usrp2')
-rw-r--r--usrp2/top/u1e/u1e_core.v19
1 files changed, 14 insertions, 5 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 4a80fe916..5c4b6de6c 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -34,7 +34,9 @@ module u1e_core
localparam SR_TX_DSP = 17; // 5 regs
localparam SR_TX_CTRL = 24; // 2 regs
localparam SR_TIME64 = 28; // 4 regs
-
+
+ wire COMPAT_NUM = 8'd2;
+
wire wb_clk = clk_fpga;
wire wb_rst = rst_fpga;
@@ -104,6 +106,8 @@ module u1e_core
wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int;
`ifdef LOOPBACK
+ wire [7:0] WHOAMI = 1;
+
fifo_cascade #(.WIDTH(36), .SIZE(12)) loopback_fifo
(.clk(wb_clk), .reset(wb_rst), .clear(clear_tx | clear_rx),
.datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
@@ -116,7 +120,8 @@ module u1e_core
`endif // LOOPBACK
`ifdef TIMED
-
+ wire [7:0] WHOAMI = 2;
+
// TX side
wire tx_enable;
@@ -147,6 +152,8 @@ module u1e_core
`endif // `ifdef TIMED
`ifdef DSP
+ wire [7:0] WHOAMI = 0;
+
wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug;
// /////////////////////////////////////////////////////////////////////////
@@ -303,9 +310,10 @@ module u1e_core
localparam REG_CGEN_CTRL = 7'd4; // out
localparam REG_CGEN_ST = 7'd6; // in
localparam REG_TEST = 7'd8; // out
- localparam REG_RX_FRAMELEN = 7'd10; // out
- localparam REG_TX_FRAMELEN = 7'd12; // in
- localparam REG_XFER_RATE = 7'd14; // in
+ localparam REG_RX_FRAMELEN = 7'd10; // in
+ localparam REG_TX_FRAMELEN = 7'd12; // out
+ localparam REG_XFER_RATE = 7'd14; // out
+ localparam REG_COMPAT = 7'd16; // in
always @(posedge wb_clk)
if(wb_rst)
@@ -344,6 +352,7 @@ module u1e_core
(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
(s0_adr[6:0] == REG_TEST) ? reg_test :
(s0_adr[6:0] == REG_RX_FRAMELEN) ? rx_frame_len :
+ (s0_adr[6:0] == REG_COMPAT) ? { WHOAMI, COMPAT_NUM } :
16'hBEEF;
assign s0_ack = s0_stb & s0_cyc;