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| author | Ian Buckley <ianb@server2.(none)> | 2010-09-14 11:46:58 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-11-11 12:10:35 -0800 |
| commit | 60a22a5273b58da49aec5c66f46738be2b7499ba (patch) | |
| tree | 24273c334fd25fbe9ca9b22eb5ac88f0ec5f8243 /usrp2 | |
| parent | 0a28cb5e7fbe81009e50fe03c4ffc3ce8db5052a (diff) | |
| download | uhd-60a22a5273b58da49aec5c66f46738be2b7499ba.tar.gz uhd-60a22a5273b58da49aec5c66f46738be2b7499ba.tar.bz2 uhd-60a22a5273b58da49aec5c66f46738be2b7499ba.zip | |
Enabled phase offset adjustment on DCM_INST1 which drives the external Fast SRAM clock.
Set phase shift to -12 after experimentation using logic analyzer to see results.
This value gives near optimum 1.5nS setup times on the source sync signals FPGA -> SRAM
under lab conditions.
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index cef868df9..faf35d12f 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -397,7 +397,7 @@ module u2_rev3 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), - .RST(clk125_ext_RST_IN), + .RST(1'b0), .CLK0(clk125_ext_clk0), .CLK180(clk125_ext_clk180) ); defparam DCM_INST1.CLK_FEEDBACK = "1X"; @@ -406,13 +406,13 @@ module u2_rev3 defparam DCM_INST1.CLKFX_MULTIPLY = 4; defparam DCM_INST1.CLKIN_DIVIDE_BY_2 = "FALSE"; defparam DCM_INST1.CLKIN_PERIOD = 8.000; - defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "NONE"; + defparam DCM_INST1.CLKOUT_PHASE_SHIFT = "FIXED"; defparam DCM_INST1.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; defparam DCM_INST1.DFS_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DLL_FREQUENCY_MODE = "LOW"; defparam DCM_INST1.DUTY_CYCLE_CORRECTION = "TRUE"; defparam DCM_INST1.FACTORY_JF = 16'h8080; - defparam DCM_INST1.PHASE_SHIFT = 0; + defparam DCM_INST1.PHASE_SHIFT = -12; defparam DCM_INST1.STARTUP_WAIT = "FALSE"; IBUFG RAM_CLK_buf_i1 (.I(RAM_CLK), @@ -431,14 +431,14 @@ module u2_rev3 .R(1'b0), .S(1'b0)); - SRL16 dcm2_rst_i1 (.D(1'b0), - .CLK(clk_to_mac_buf), - .Q(dcm2_rst), - .A0(1'b1), - .A1(1'b1), - .A2(1'b1), - .A3(1'b1)); - // synthesis attribute init of dcm2_rst_i2 is "000F"; +// SRL16 dcm2_rst_i1 (.D(1'b0), +// .CLK(clk_to_mac_buf), +// .Q(dcm2_rst), +// .A0(1'b1), +// .A1(1'b1), +// .A2(1'b1), +// .A3(1'b1)); + // synthesis attribute init of dcm2_rst_i1 is "000F"; DCM DCM_INST2 (.CLKFB(clk125_int_buf), .CLKIN(clk_to_mac_buf), @@ -446,7 +446,7 @@ module u2_rev3 .PSCLK(1'b0), .PSEN(1'b0), .PSINCDEC(1'b0), - .RST(clk125_int_RST_IN), + .RST(1'b0), .CLK0(clk125_int)); defparam DCM_INST2.CLK_FEEDBACK = "1X"; defparam DCM_INST2.CLKDV_DIVIDE = 2.0; |