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| author | Matt Ettus <matt@ettus.com> | 2010-07-09 14:21:48 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-09 14:21:48 -0700 |
| commit | 42a98490a78ab08615dafe688848010c1a97ccfe (patch) | |
| tree | 5f161d37dd9d7b81cb00c3e50fafa0f8c28804d8 /usrp2 | |
| parent | 7c50d20eb44f93e29669dc383f056e692f1654f3 (diff) | |
| download | uhd-42a98490a78ab08615dafe688848010c1a97ccfe.tar.gz uhd-42a98490a78ab08615dafe688848010c1a97ccfe.tar.bz2 uhd-42a98490a78ab08615dafe688848010c1a97ccfe.zip | |
updated tests to match new features
Diffstat (limited to 'usrp2')
| -rwxr-xr-x | usrp2/vrt/vita_rx.build | 2 | ||||
| -rw-r--r-- | usrp2/vrt/vita_rx_tb.v | 11 |
2 files changed, 9 insertions, 4 deletions
diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build index f6d2d75a3..010d1be6e 100755 --- a/usrp2/vrt/vita_rx.build +++ b/usrp2/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v diff --git a/usrp2/vrt/vita_rx_tb.v b/usrp2/vrt/vita_rx_tb.v index b4fda9622..3e01e2ee2 100644 --- a/usrp2/vrt/vita_rx_tb.v +++ b/usrp2/vrt/vita_rx_tb.v @@ -3,8 +3,8 @@ module vita_rx_tb; localparam DECIM = 8'd4; - localparam MAXCHAN=4; - localparam NUMCHAN=4; + localparam MAXCHAN=1; + localparam NUMCHAN=1; reg clk = 0; reg reset = 1; @@ -94,7 +94,7 @@ module vita_rx_tb; @(posedge clk); write_setting(4,32'hDEADBEEF); // VITA header write_setting(5,32'hF00D1234); // VITA streamid - write_setting(6,32'h98765432); // VITA trailer + write_setting(6,32'hF0000000); // VITA trailer write_setting(7,8); // Samples per VITA packet write_setting(8,NUMCHAN); // Samples per VITA packet queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet @@ -111,8 +111,13 @@ module vita_rx_tb; queue_rx_cmd(0,0,8,32'h0,32'h340); // send at, on time queue_rx_cmd(0,0,8,32'h0,32'h100); // send at, but late + #100000; + $display("\nChained, break chain\n"); queue_rx_cmd(1,1,8,32'h0,32'h0); // chained, but break chain #100000; + $display("\nSingle packet\n"); + queue_rx_cmd(1,0,8,32'h0,32'h0); // send imm, single packet + #100000; $display("\nEnd chain with zero samples, shouldn't error\n"); queue_rx_cmd(1,1,8,32'h0,32'h0); // chained queue_rx_cmd(0,0,0,32'h0,32'h0); // end chain with zero samples, should keep us out of error |