packet_router: created packet dispatcher component to replace packet inspector in router

3 files changed, 293 insertions, 236 deletions

diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
index c1287cd5c..31b1f505a 100644
--- a/usrp2/fifo/Makefile.srcs
+++ b/usrp2/fifo/Makefile.srcs
@@ -29,6 +29,7 @@ packet_router.v \
 splitter36.v \
 valve36.v \
 fifo_pacer.v \
+packet_dispatcher36_x3.v \
 packet_generator32.v \
 packet_generator.v \
 packet_verifier32.v \
diff --git a/usrp2/fifo/packet_dispatcher36_x3.v b/usrp2/fifo/packet_dispatcher36_x3.v
new file mode 100644
index 000000000..fd762d061
--- /dev/null
+++ b/usrp2/fifo/packet_dispatcher36_x3.v
@@ -0,0 +1,270 @@
+//
+// Copyright 2011 Ettus Research LLC
+//
+// Packet dispatcher with fifo36 interface and 3 outputs.
+//
+// The packet dispatcher expects 2-byte padded ethernet frames.
+// The frames will be inspected at ethernet, IPv4, UDP, and VRT layers.
+// Packets are dispatched into the following streams:
+//   * tx dsp stream
+//   * to cpu stream
+//   * to external stream
+//   * to both cpu and external
+//
+// The following registers are used for dispatcher control:
+//   * base + 0 = this ipv4 address (32 bits)
+//   * base + 1 = udp dst port (lower 16 bits)
+//
+
+module packet_dispatcher36_x3
+    #(
+        parameter BASE = 0
+    )
+    (
+        //clocking and reset interface:
+        input clk, input rst, input clr,
+
+        //setting register interface:
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        //input stream interfaces:
+        input [35:0] com_inp_data, input com_inp_valid, output com_inp_ready,
+
+        //output stream interfaces:
+        output [35:0] ext_out_data, output ext_out_valid, input ext_out_ready,
+        output [35:0] dsp_out_data, output dsp_out_valid, input dsp_out_ready,
+        output [35:0] cpu_out_data, output cpu_out_valid, input cpu_out_ready
+    );
+
+    //setting register to program the IP address
+    wire [31:0] my_ip_addr;
+    setting_reg #(.my_addr(BASE+0)) sreg_ip_addr(
+        .clk(clk),.rst(rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(my_ip_addr),.changed()
+    );
+
+    //setting register to program the UDP DSP port
+    wire [15:0] dsp_udp_port;
+    setting_reg #(.my_addr(BASE+1), .width(16)) sreg_data_port(
+        .clk(clk),.rst(rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(dsp_udp_port),.changed()
+    );
+
+    ////////////////////////////////////////////////////////////////////
+    // Communication input inspector
+    //   - inspect com input and send it to DSP, EXT, CPU, or BOTH
+    ////////////////////////////////////////////////////////////////////
+    localparam PD_STATE_READ_COM_PRE = 0;
+    localparam PD_STATE_READ_COM = 1;
+    localparam PD_STATE_WRITE_REGS = 2;
+    localparam PD_STATE_WRITE_LIVE = 3;
+
+    localparam PD_DEST_DSP = 0;
+    localparam PD_DEST_EXT = 1;
+    localparam PD_DEST_CPU = 2;
+    localparam PD_DEST_BOF = 3;
+
+    localparam PD_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
+    localparam PD_DREGS_DSP_OFFSET = 11; //offset to start dsp at
+
+    //output inspector interfaces
+    wire [35:0] pd_out_dsp_data;
+    wire        pd_out_dsp_valid;
+    wire        pd_out_dsp_ready;
+
+    wire [35:0] pd_out_ext_data;
+    wire        pd_out_ext_valid;
+    wire        pd_out_ext_ready;
+
+    wire [35:0] pd_out_cpu_data;
+    wire        pd_out_cpu_valid;
+    wire        pd_out_cpu_ready;
+
+    wire [35:0] pd_out_bof_data;
+    wire        pd_out_bof_valid;
+    wire        pd_out_bof_ready;
+
+    reg [1:0] pd_state;
+    reg [1:0] pd_dest;
+    reg [3:0] pd_dreg_count; //data registers to buffer headers
+    wire [3:0] pd_dreg_count_next = pd_dreg_count + 1'b1;
+    wire pd_dreg_counter_done = (pd_dreg_count_next == PD_MAX_NUM_DREGS)? 1'b1 : 1'b0;
+    reg [35:0] pd_dregs [PD_MAX_NUM_DREGS-1:0];
+
+    //extract various packet components:
+    wire [47:0] pd_dregs_eth_dst_mac   = {pd_dregs[0][15:0], pd_dregs[1][31:0]};
+    wire [15:0] pd_dregs_eth_type      = pd_dregs[3][15:0];
+    wire [7:0]  pd_dregs_ipv4_proto    = pd_dregs[6][23:16];
+    wire [31:0] pd_dregs_ipv4_dst_addr = pd_dregs[8][31:0];
+    wire [15:0] pd_dregs_udp_dst_port  = pd_dregs[9][15:0];
+    wire [15:0] pd_dregs_vrt_size      = com_inp_data[15:0];
+
+    //Inspector output flags special case:
+    //Inject SOF into flags at first DSP line.
+    wire [3:0] pd_out_flags = (
+        (pd_dreg_count == PD_DREGS_DSP_OFFSET) &&
+        (pd_dest == PD_DEST_DSP)
+    )? 4'b0001 : pd_dregs[pd_dreg_count][35:32];
+
+    //The communication inspector ouput data and valid signals:
+    //Mux between com input and data registers based on the state.
+    wire [35:0] pd_out_data = (pd_state == PD_STATE_WRITE_REGS)?
+        {pd_out_flags, pd_dregs[pd_dreg_count][31:0]} : com_inp_data
+    ;
+    wire pd_out_valid =
+        (pd_state == PD_STATE_WRITE_REGS)? 1'b1          : (
+        (pd_state == PD_STATE_WRITE_LIVE)? com_inp_valid : (
+    1'b0));
+
+    //The communication inspector ouput ready signal:
+    //Mux between the various destination ready signals.
+    wire pd_out_ready =
+        (pd_dest == PD_DEST_DSP)? pd_out_dsp_ready : (
+        (pd_dest == PD_DEST_EXT)? pd_out_ext_ready : (
+        (pd_dest == PD_DEST_CPU)? pd_out_cpu_ready : (
+        (pd_dest == PD_DEST_BOF)? pd_out_bof_ready : (
+    1'b0))));
+
+    //Always connected output data lines.
+    assign pd_out_dsp_data = pd_out_data;
+    assign pd_out_ext_data = pd_out_data;
+    assign pd_out_cpu_data = pd_out_data;
+    assign pd_out_bof_data = pd_out_data;
+
+    //Destination output valid signals:
+    //Comes from inspector valid when destination is selected, and otherwise low.
+    assign pd_out_dsp_valid = (pd_dest == PD_DEST_DSP)? pd_out_valid : 1'b0;
+    assign pd_out_ext_valid = (pd_dest == PD_DEST_EXT)? pd_out_valid : 1'b0;
+    assign pd_out_cpu_valid = (pd_dest == PD_DEST_CPU)? pd_out_valid : 1'b0;
+    assign pd_out_bof_valid = (pd_dest == PD_DEST_BOF)? pd_out_valid : 1'b0;
+
+    //The communication inspector ouput ready signal:
+    //Always ready when storing to data registers,
+    //comes from inspector ready output when live,
+    //and otherwise low.
+    assign com_inp_ready =
+        (pd_state == PD_STATE_READ_COM_PRE)  ? 1'b1         : (
+        (pd_state == PD_STATE_READ_COM)      ? 1'b1         : (
+        (pd_state == PD_STATE_WRITE_LIVE)    ? pd_out_ready : (
+    1'b0)));
+
+    always @(posedge clk)
+    if(rst | clr) begin
+        pd_state <= PD_STATE_READ_COM_PRE;
+        pd_dreg_count <= 0;
+    end
+    else begin
+        case(pd_state)
+        PD_STATE_READ_COM_PRE: begin
+            if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin
+                pd_state <= PD_STATE_READ_COM;
+                pd_dreg_count <= pd_dreg_count_next;
+                pd_dregs[pd_dreg_count] <= com_inp_data;
+            end
+        end
+
+        PD_STATE_READ_COM: begin
+            if (com_inp_ready & com_inp_valid) begin
+                pd_dregs[pd_dreg_count] <= com_inp_data;
+                if (pd_dreg_counter_done | com_inp_data[33]) begin
+                    pd_state <= PD_STATE_WRITE_REGS;
+                    pd_dreg_count <= 0;
+
+                    //---------- begin inspection decision -----------//
+                    //EOF or bcast or not IPv4 or not UDP:
+                    if (
+                        com_inp_data[33] || (pd_dregs_eth_dst_mac == 48'hffffffffffff) ||
+                        (pd_dregs_eth_type != 16'h800) || (pd_dregs_ipv4_proto != 8'h11)
+                    ) begin
+                        pd_dest <= PD_DEST_BOF;
+                    end
+
+                    //not my IP address:
+                    else if (pd_dregs_ipv4_dst_addr != my_ip_addr) begin
+                        pd_dest <= PD_DEST_EXT;
+                    end
+
+                    //UDP data port and VRT:
+                    else if ((pd_dregs_udp_dst_port == dsp_udp_port) && (pd_dregs_vrt_size != 16'h0)) begin
+                        pd_dest <= PD_DEST_DSP;
+                        pd_dreg_count <= PD_DREGS_DSP_OFFSET;
+                    end
+
+                    //other:
+                    else begin
+                        pd_dest <= PD_DEST_CPU;
+                    end
+                    //---------- end inspection decision -------------//
+
+                end
+                else begin
+                    pd_dreg_count <= pd_dreg_count_next;
+                end
+            end
+        end
+
+        PD_STATE_WRITE_REGS: begin
+            if (pd_out_ready & pd_out_valid) begin
+                if (pd_out_data[33]) begin
+                    pd_state <= PD_STATE_READ_COM_PRE;
+                    pd_dreg_count <= 0;
+                end
+                else if (pd_dreg_counter_done) begin
+                    pd_state <= PD_STATE_WRITE_LIVE;
+                    pd_dreg_count <= 0;
+                end
+                else begin
+                    pd_dreg_count <= pd_dreg_count_next;
+                end
+            end
+        end
+
+        PD_STATE_WRITE_LIVE: begin
+            if (pd_out_ready & pd_out_valid & pd_out_data[33]) begin
+                pd_state <= PD_STATE_READ_COM_PRE;
+            end
+        end
+
+        endcase //pd_state
+    end
+
+    //connect this fast-path signals directly to the DSP out
+    assign dsp_out_data = pd_out_dsp_data;
+    assign dsp_out_valid = pd_out_dsp_valid;
+    assign pd_out_dsp_ready = dsp_out_ready;
+
+    ////////////////////////////////////////////////////////////////////
+    // Splitter and output muxes for the bof packets
+    //   - split the bof packets into two streams
+    //   - mux split packets into cpu out and ext out
+    ////////////////////////////////////////////////////////////////////
+
+    //dummy signals to join the the splitter and muxes below
+    wire [35:0] _split_to_ext_data,  _split_to_cpu_data;
+    wire        _split_to_ext_valid, _split_to_cpu_valid;
+    wire        _split_to_ext_ready, _split_to_cpu_ready;
+
+    splitter36 bof_out_splitter(
+        .clk(clk), .rst(rst), .clr(clr),
+        .inp_data(pd_out_bof_data), .inp_valid(pd_out_bof_valid), .inp_ready(pd_out_bof_ready),
+        .out0_data(_split_to_ext_data), .out0_valid(_split_to_ext_valid), .out0_ready(_split_to_ext_ready),
+        .out1_data(_split_to_cpu_data), .out1_valid(_split_to_cpu_valid), .out1_ready(_split_to_cpu_ready)
+    );
+
+    fifo36_mux ext_out_mux(
+        .clk(clk), .reset(rst), .clear(clr),
+        .data0_i(pd_out_ext_data), .src0_rdy_i(pd_out_ext_valid), .dst0_rdy_o(pd_out_ext_ready),
+        .data1_i(_split_to_ext_data), .src1_rdy_i(_split_to_ext_valid), .dst1_rdy_o(_split_to_ext_ready),
+        .data_o(ext_out_data), .src_rdy_o(ext_out_valid), .dst_rdy_i(ext_out_ready)
+    );
+
+    fifo36_mux cpu_out_mux(
+        .clk(clk), .reset(rst), .clear(clr),
+        .data0_i(pd_out_cpu_data), .src0_rdy_i(pd_out_cpu_valid), .dst0_rdy_o(pd_out_cpu_ready),
+        .data1_i(_split_to_cpu_data), .src1_rdy_i(_split_to_cpu_valid), .dst1_rdy_o(_split_to_cpu_ready),
+        .data_o(cpu_out_data), .src_rdy_o(cpu_out_valid), .dst_rdy_i(cpu_out_ready)
+    );
+
+endmodule // packet_dispatcher36_x3
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
index d0ddb2784..7774ff076 100644
--- a/usrp2/fifo/packet_router.v
+++ b/usrp2/fifo/packet_router.v
@@ -69,7 +69,7 @@ module packet_router
 
     //setting register for mode control
     wire [31:0] _sreg_mode_ctrl;
-    wire 	master_mode_flag;
+    wire        master_mode_flag;
    
     setting_reg #(.my_addr(CTRL_BASE+0), .width(1)) sreg_mode_ctrl(
         .clk(stream_clk),.rst(stream_rst),
@@ -77,22 +77,6 @@ module packet_router
         .out(master_mode_flag),.changed()
     );
 
-    //setting register to program the IP address
-    wire [31:0] my_ip_addr;
-    setting_reg #(.my_addr(CTRL_BASE+1)) sreg_ip_addr(
-        .clk(stream_clk),.rst(stream_rst),
-        .strobe(set_stb),.addr(set_addr),.in(set_data),
-        .out(my_ip_addr),.changed()
-    );
-
-    //setting register to program the UDP data ports
-    wire [15:0] dsp_udp_port;
-    setting_reg #(.my_addr(CTRL_BASE+2), .width(16)) sreg_data_ports(
-        .clk(stream_clk),.rst(stream_rst),
-        .strobe(set_stb),.addr(set_addr),.in(set_data),
-        .out(dsp_udp_port),.changed()
-    );
-
     //assign status output signals
     wire [31:0] cpu_iface_status;
     assign status = {
@@ -120,8 +104,8 @@ module packet_router
     wire        _eth_inp_ready;
 
     // dummy signals to connect fifo_short
-    wire [35:0]	_com_inp_data;
-    wire 	_com_inp_valid;
+    wire [35:0] _com_inp_data;
+    wire        _com_inp_valid;
     wire        _com_inp_ready;
 
     valve36 eth_inp_valve (
@@ -217,6 +201,7 @@ module packet_router
 
     ////////////////////////////////////////////////////////////////////
     // Interface CPU to memory mapped wishbone
+    //   - Uses 1 setting register
     ////////////////////////////////////////////////////////////////////
     buffer_int2 #(.BASE(CTRL_BASE+3), .BUF_SIZE(BUF_SIZE)) cpu_to_wb(
         .clk(stream_clk), .rst(stream_rst | stream_clr),
@@ -238,218 +223,21 @@ module packet_router
     );
 
     ////////////////////////////////////////////////////////////////////
-    // Communication input inspector
-    //   - inspect com input and send it to DSP, EXT, CPU, or BOTH
-    ////////////////////////////////////////////////////////////////////
-    localparam COM_INSP_STATE_READ_COM_PRE = 0;
-    localparam COM_INSP_STATE_READ_COM = 1;
-    localparam COM_INSP_STATE_WRITE_REGS = 2;
-    localparam COM_INSP_STATE_WRITE_LIVE = 3;
-
-    localparam COM_INSP_DEST_DSP = 0;
-    localparam COM_INSP_DEST_EXT = 1;
-    localparam COM_INSP_DEST_CPU = 2;
-    localparam COM_INSP_DEST_BOF = 3;
-
-    localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
-    localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at
-
-    //output inspector interfaces
-    wire [35:0] com_insp_out_dsp_data;
-    wire        com_insp_out_dsp_valid;
-    wire        com_insp_out_dsp_ready;
-
-    wire [35:0] com_insp_out_ext_data;
-    wire        com_insp_out_ext_valid;
-    wire        com_insp_out_ext_ready;
-
-    wire [35:0] com_insp_out_cpu_data;
-    wire        com_insp_out_cpu_valid;
-    wire        com_insp_out_cpu_ready;
-
-    wire [35:0] com_insp_out_bof_data;
-    wire        com_insp_out_bof_valid;
-    wire        com_insp_out_bof_ready;
-
-    //connect this fast-path signals directly to the DSP out
-    assign dsp_out_data = com_insp_out_dsp_data;
-    assign dsp_out_valid = com_insp_out_dsp_valid;
-    assign com_insp_out_dsp_ready = dsp_out_ready;
-
-    reg [1:0] com_insp_state;
-    reg [1:0] com_insp_dest;
-    reg [3:0] com_insp_dreg_count; //data registers to buffer headers
-    wire [3:0] com_insp_dreg_count_next = com_insp_dreg_count + 1'b1;
-    wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0;
-    reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0];
-
-    //extract various packet components:
-    wire [47:0] com_insp_dregs_eth_dst_mac   = {com_insp_dregs[0][15:0], com_insp_dregs[1][31:0]};
-    wire [15:0] com_insp_dregs_eth_type      = com_insp_dregs[3][15:0];
-    wire [7:0]  com_insp_dregs_ipv4_proto    = com_insp_dregs[6][23:16];
-    wire [31:0] com_insp_dregs_ipv4_dst_addr = com_insp_dregs[8][31:0];
-    wire [15:0] com_insp_dregs_udp_dst_port  = com_insp_dregs[9][15:0];
-    wire [15:0] com_insp_dregs_vrt_size      = com_inp_data[15:0];
-
-    //Inspector output flags special case:
-    //Inject SOF into flags at first DSP line.
-    wire [3:0] com_insp_out_flags = (
-        (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) &&
-        (com_insp_dest == COM_INSP_DEST_DSP)
-    )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32];
-
-    //The communication inspector ouput data and valid signals:
-    //Mux between com input and data registers based on the state.
-    wire [35:0] com_insp_out_data = (com_insp_state == COM_INSP_STATE_WRITE_REGS)?
-        {com_insp_out_flags, com_insp_dregs[com_insp_dreg_count][31:0]} : com_inp_data
-    ;
-    wire com_insp_out_valid =
-        (com_insp_state == COM_INSP_STATE_WRITE_REGS)? 1'b1          : (
-        (com_insp_state == COM_INSP_STATE_WRITE_LIVE)? com_inp_valid : (
-    1'b0));
-
-    //The communication inspector ouput ready signal:
-    //Mux between the various destination ready signals.
-    wire com_insp_out_ready =
-        (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_dsp_ready : (
-        (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_ext_ready : (
-        (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_cpu_ready : (
-        (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_bof_ready : (
-    1'b0))));
-
-    //Always connected output data lines.
-    assign com_insp_out_dsp_data = com_insp_out_data;
-    assign com_insp_out_ext_data = com_insp_out_data;
-    assign com_insp_out_cpu_data = com_insp_out_data;
-    assign com_insp_out_bof_data = com_insp_out_data;
-
-    //Destination output valid signals:
-    //Comes from inspector valid when destination is selected, and otherwise low.
-    assign com_insp_out_dsp_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0;
-    assign com_insp_out_ext_valid = (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_valid : 1'b0;
-    assign com_insp_out_cpu_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0;
-    assign com_insp_out_bof_valid = (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_valid : 1'b0;
-
-    //The communication inspector ouput ready signal:
-    //Always ready when storing to data registers,
-    //comes from inspector ready output when live,
-    //and otherwise low.
-    assign com_inp_ready =
-        (com_insp_state == COM_INSP_STATE_READ_COM_PRE)  ? 1'b1               : (
-        (com_insp_state == COM_INSP_STATE_READ_COM)      ? 1'b1               : (
-        (com_insp_state == COM_INSP_STATE_WRITE_LIVE)    ? com_insp_out_ready : (
-    1'b0)));
-
-    always @(posedge stream_clk)
-    if(stream_rst | stream_clr) begin
-        com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
-        com_insp_dreg_count <= 0;
-    end
-    else begin
-        case(com_insp_state)
-        COM_INSP_STATE_READ_COM_PRE: begin
-            if (com_inp_ready & com_inp_valid & com_inp_data[32]) begin
-                com_insp_state <= COM_INSP_STATE_READ_COM;
-                com_insp_dreg_count <= com_insp_dreg_count_next;
-                com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
-            end
-        end
-
-        COM_INSP_STATE_READ_COM: begin
-            if (com_inp_ready & com_inp_valid) begin
-                com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
-                if (com_insp_dreg_counter_done | com_inp_data[33]) begin
-                    com_insp_state <= COM_INSP_STATE_WRITE_REGS;
-                    com_insp_dreg_count <= 0;
-
-                    //---------- begin inspection decision -----------//
-                    //EOF or bcast or not IPv4 or not UDP:
-                    if (
-                        com_inp_data[33] || (com_insp_dregs_eth_dst_mac == 48'hffffffffffff) ||
-                        (com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11)
-                    ) begin
-                        com_insp_dest <= COM_INSP_DEST_BOF;
-                    end
-
-                    //not my IP address:
-                    else if (com_insp_dregs_ipv4_dst_addr != my_ip_addr) begin
-                        com_insp_dest <= COM_INSP_DEST_EXT;
-                    end
-
-                    //UDP data port and VRT:
-                    else if ((com_insp_dregs_udp_dst_port == dsp_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin
-                        com_insp_dest <= COM_INSP_DEST_DSP;
-                        com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET;
-                    end
-
-                    //other:
-                    else begin
-                        com_insp_dest <= COM_INSP_DEST_CPU;
-                    end
-                    //---------- end inspection decision -------------//
-
-                end
-                else begin
-                    com_insp_dreg_count <= com_insp_dreg_count_next;
-                end
-            end
-        end
-
-        COM_INSP_STATE_WRITE_REGS: begin
-            if (com_insp_out_ready & com_insp_out_valid) begin
-                if (com_insp_out_data[33]) begin
-                    com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
-                    com_insp_dreg_count <= 0;
-                end
-                else if (com_insp_dreg_counter_done) begin
-                    com_insp_state <= COM_INSP_STATE_WRITE_LIVE;
-                    com_insp_dreg_count <= 0;
-                end
-                else begin
-                    com_insp_dreg_count <= com_insp_dreg_count_next;
-                end
-            end
-        end
-
-        COM_INSP_STATE_WRITE_LIVE: begin
-            if (com_insp_out_ready & com_insp_out_valid & com_insp_out_data[33]) begin
-                com_insp_state <= COM_INSP_STATE_READ_COM_PRE;
-            end
-        end
-
-        endcase //com_insp_state
-    end
-
-    ////////////////////////////////////////////////////////////////////
-    // Splitter and output muxes for the bof packets
-    //   - split the bof packets into two streams
-    //   - mux split packets into cpu out and ext out
+    // Packet Dispatcher
+    //   - Uses 2 setting registers
+    //   - provide buffering before cpu for random + small packet bursts
     ////////////////////////////////////////////////////////////////////
+    wire [35:0] _cpu_out_data;
+    wire        _cpu_out_valid;
+    wire        _cpu_out_ready;
 
-    //dummy signals to join the the splitter and muxes below
-    wire [35:0] _split_to_ext_data,  _split_to_cpu_data,  _cpu_out_data;
-    wire        _split_to_ext_valid, _split_to_cpu_valid, _cpu_out_valid;
-    wire        _split_to_ext_ready, _split_to_cpu_ready, _cpu_out_ready;
-
-    splitter36 bof_out_splitter(
+    packet_dispatcher36_x3 #(.BASE(CTRL_BASE+1)) packet_dispatcher(
         .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
-        .inp_data(com_insp_out_bof_data), .inp_valid(com_insp_out_bof_valid), .inp_ready(com_insp_out_bof_ready),
-        .out0_data(_split_to_ext_data),   .out0_valid(_split_to_ext_valid),   .out0_ready(_split_to_ext_ready),
-        .out1_data(_split_to_cpu_data),   .out1_valid(_split_to_cpu_valid),   .out1_ready(_split_to_cpu_ready)
-    );
-
-    fifo36_mux ext_out_mux(
-        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(com_insp_out_ext_data), .src0_rdy_i(com_insp_out_ext_valid), .dst0_rdy_o(com_insp_out_ext_ready),
-        .data1_i(_split_to_ext_data),    .src1_rdy_i(_split_to_ext_valid),    .dst1_rdy_o(_split_to_ext_ready),
-        .data_o(ext_out_data),           .src_rdy_o(ext_out_valid),           .dst_rdy_i(ext_out_ready)
-    );
-
-    fifo36_mux cpu_out_mux(
-        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(com_insp_out_cpu_data), .src0_rdy_i(com_insp_out_cpu_valid), .dst0_rdy_o(com_insp_out_cpu_ready),
-        .data1_i(_split_to_cpu_data),    .src1_rdy_i(_split_to_cpu_valid),    .dst1_rdy_o(_split_to_cpu_ready),
-        .data_o(_cpu_out_data),          .src_rdy_o(_cpu_out_valid),          .dst_rdy_i(_cpu_out_ready)
+        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+        .com_inp_data(com_inp_data), .com_inp_valid(com_inp_valid), .com_inp_ready(com_inp_ready),
+        .ext_out_data(ext_out_data), .ext_out_valid(ext_out_valid), .ext_out_ready(ext_out_ready),
+        .dsp_out_data(dsp_out_data), .dsp_out_valid(dsp_out_valid), .dsp_out_ready(dsp_out_ready),
+        .cpu_out_data(_cpu_out_data), .cpu_out_valid(_cpu_out_valid), .cpu_out_ready(_cpu_out_ready)
     );
 
     fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) cpu_out_fifo (
@@ -498,8 +286,10 @@ module packet_router
     ////////////////////////////////////////////////////////////////////
 
     assign debug = {
-        //inputs to the router (8)
+        //inputs to the router (12)
         dsp0_inp_ready, dsp0_inp_valid,
+        dsp1_inp_ready, dsp1_inp_valid,
+        err_inp_ready, err_inp_valid,
         ser_inp_ready, ser_inp_valid,
         eth_inp_ready, eth_inp_valid,
         cpu_inp_ready, cpu_inp_valid,
@@ -510,17 +300,13 @@ module packet_router
         eth_out_ready, eth_out_valid,
         cpu_out_ready, cpu_out_valid,
 
-        //inspector interfaces (8)
-        com_insp_out_dsp_ready, com_insp_out_dsp_valid,
-        com_insp_out_ext_ready, com_insp_out_ext_valid,
-        com_insp_out_cpu_ready, com_insp_out_cpu_valid,
-        com_insp_out_bof_ready, com_insp_out_bof_valid,
-
         //other interfaces (8)
         ext_inp_ready, ext_inp_valid,
         com_out_ready, com_out_valid,
         ext_out_ready, ext_out_valid,
-        com_inp_ready, com_inp_valid
+        com_inp_ready, com_inp_valid,
+
+        4'b0
     };
 
 endmodule // packet_router