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| author | Matt Ettus <matt@ettus.com> | 2010-07-09 14:20:30 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-09 14:20:30 -0700 |
| commit | c3ef4c04fd8d887a733fa9a8ed5b6702cf453a01 (patch) | |
| tree | e8c2a39ec4858cd0c41b239405c890c6281b8947 /usrp2 | |
| parent | 455e9540c6716a26f064871f691c102ac758ebc6 (diff) | |
| download | uhd-c3ef4c04fd8d887a733fa9a8ed5b6702cf453a01.tar.gz uhd-c3ef4c04fd8d887a733fa9a8ed5b6702cf453a01.tar.bz2 uhd-c3ef4c04fd8d887a733fa9a8ed5b6702cf453a01.zip | |
point to new location for fifos
Diffstat (limited to 'usrp2')
| -rwxr-xr-x | usrp2/vrt/vita_rx.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build index f6d2d75a3..010d1be6e 100755 --- a/usrp2/vrt/vita_rx.build +++ b/usrp2/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v |