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| author | Matt Ettus <matt@ettus.com> | 2011-03-03 11:26:29 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-03 11:26:29 -0800 |
| commit | 6a8f7025044dd002fa1242cc10da536f1d6ad007 (patch) | |
| tree | e12f9dcd01060ebf22d93ecf47d59e10f668938e /usrp2 | |
| parent | 6cbbabde84c0e6e1396b6e26ee888cdcbe762caf (diff) | |
| download | uhd-6a8f7025044dd002fa1242cc10da536f1d6ad007.tar.gz uhd-6a8f7025044dd002fa1242cc10da536f1d6ad007.tar.bz2 uhd-6a8f7025044dd002fa1242cc10da536f1d6ad007.zip | |
u2/u2p: packet realignment moved into the simple_gemac_wrapper19
Diffstat (limited to 'usrp2')
| -rw-r--r-- | usrp2/simple_gemac/simple_gemac_wrapper19.v | 13 | ||||
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 10 |
2 files changed, 10 insertions, 13 deletions
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.v b/usrp2/simple_gemac/simple_gemac_wrapper19.v index 516cb3e2a..c155b7d41 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -70,8 +70,8 @@ module simple_gemac_wrapper19 wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; wire [7:0] rx_ll_data; - wire [18:0] rx_f19_data_int1; - wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1; + wire [18:0] rx_f19_data_int1, rx_f19_data_int2; + wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2; rxmac_to_ll8 rx_adapt (.clk(rx_clk), .reset(rx_reset), .clear(0), @@ -85,10 +85,15 @@ module simple_gemac_wrapper19 .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy), .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1)); + fifo19_rxrealign fifo19_rxrealign + (.clk(rx_clk), .reset(rx_reset), .clear(0), + .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), + .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) ); + //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo - (.wclk(rx_clk), .datain(rx_f19_data_int1), - .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1), .space(rx_fifo_space), + (.wclk(rx_clk), .datain(rx_f19_data_int2), + .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space), .rclk(sys_clk), .dataout(rx_f19_data), .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), .arst(reset)); diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index 10bfd5ffb..5652673be 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -453,18 +453,10 @@ module u2_core wire [35:0] rx_f36_data, tx_f36_data; wire rx_f36_src_rdy, rx_f36_dst_rdy, tx_f36_src_rdy, tx_f36_dst_rdy; - wire [18:0] _rx_f19_data; - wire _rx_f19_src_rdy, _rx_f19_dst_rdy; - //mac rx to eth input... - fifo19_rxrealign fifo19_rxrealign - (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .datain(rx_f19_data), .src_rdy_i(rx_f19_src_rdy), .dst_rdy_o(rx_f19_dst_rdy), - .dataout(_rx_f19_data), .src_rdy_o(_rx_f19_src_rdy), .dst_rdy_i(_rx_f19_dst_rdy) ); - fifo19_to_fifo36 eth_inp_fifo19_to_fifo36 (.clk(dsp_clk), .reset(dsp_rst), .clear(0), - .f19_datain(_rx_f19_data), .f19_src_rdy_i(_rx_f19_src_rdy), .f19_dst_rdy_o(_rx_f19_dst_rdy), + .f19_datain(rx_f19_data), .f19_src_rdy_i(rx_f19_src_rdy), .f19_dst_rdy_o(rx_f19_dst_rdy), .f36_dataout(rx_f36_data), .f36_src_rdy_o(rx_f36_src_rdy), .f36_dst_rdy_i(rx_f36_dst_rdy) ); fifo_cascade #(.WIDTH(36), .SIZE(ETH_RX_FIFOSIZE)) rx_eth_fifo |