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author | Matt Ettus <matt@ettus.com> | 2010-07-29 12:22:13 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-07-29 12:22:13 -0700 |
commit | c174bf9acb2b2d142456f1186bd3e41e40d8a6d1 (patch) | |
tree | 9013f1208ec463d2712cccd83c9a6ff32ee1dc44 /usrp2 | |
parent | 41f9748a2d856aa3d1fe7b895e38ad3c4b65e11e (diff) | |
download | uhd-c174bf9acb2b2d142456f1186bd3e41e40d8a6d1.tar.gz uhd-c174bf9acb2b2d142456f1186bd3e41e40d8a6d1.tar.bz2 uhd-c174bf9acb2b2d142456f1186bd3e41e40d8a6d1.zip |
provide a way to get out of the error state without processor intervention
Diffstat (limited to 'usrp2')
-rw-r--r-- | usrp2/vrt/vita_tx_control.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index 35b6de4f0..d0516bec8 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -143,7 +143,10 @@ module vita_tx_control end IBS_ERROR_DONE : - send_error <= 0; + begin + send_error <= 0; + ibs_state <= IBS_IDLE; + end IBS_ERROR_WAIT : send_error <= 0; |