simple_gemac: remove old 19-bit wide wrapper

4 files changed, 0 insertions, 402 deletions

diff --git a/usrp2/simple_gemac/Makefile.srcs b/usrp2/simple_gemac/Makefile.srcs
index 7bcc58c91..4ba3852b0 100644
--- a/usrp2/simple_gemac/Makefile.srcs
+++ b/usrp2/simple_gemac/Makefile.srcs
@@ -7,7 +7,6 @@
 ##################################################
 SIMPLE_GEMAC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../simple_gemac/, \
 simple_gemac_wrapper.v \
-simple_gemac_wrapper19.v \
 simple_gemac.v \
 simple_gemac_wb.v \
 simple_gemac_tx.v \
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.build b/usrp2/simple_gemac/simple_gemac_wrapper19.build
deleted file mode 100755
index b9475baa2..000000000
--- a/usrp2/simple_gemac/simple_gemac_wrapper19.build
+++ /dev/null
@@ -1 +0,0 @@
-iverilog -Wimplict -Wportbind -y ../fifo/ -y ../models/ -y . -y miim -y ../coregen/ -y ../control_lib/ -o simple_gemac_wrapper19_tb simple_gemac_wrapper19_tb.v
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.v b/usrp2/simple_gemac/simple_gemac_wrapper19.v
deleted file mode 100644
index 3e1793d82..000000000
--- a/usrp2/simple_gemac/simple_gemac_wrapper19.v
+++ /dev/null
@@ -1,174 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-
-module simple_gemac_wrapper19
-  #(parameter RXFIFOSIZE=9,
-    parameter TXFIFOSIZE=6)
-   (input clk125, input reset,
-    // GMII
-    output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
-    input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
-    
-    // Client FIFO Interfaces
-    input sys_clk,
-    output [18:0] rx_f19_data, output rx_f19_src_rdy, input rx_f19_dst_rdy,
-    input [18:0] tx_f19_data, input tx_f19_src_rdy, output tx_f19_dst_rdy,
-    
-    // Wishbone Interface
-    input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
-    input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
-    
-    // MIIM
-    inout mdio, output mdc,
-    output [31:0] debug);
-
-   wire 	  clear = 0;
-   wire [7:0] 	  rx_data, tx_data;
-   wire 	  tx_clk, tx_valid, tx_error, tx_ack;
-   wire 	  rx_clk, rx_valid, rx_error, rx_ack;
-   
-   wire [47:0] 	  ucast_addr, mcast_addr;
-   wire 	  pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
-   wire 	  pause_req;
-   wire 	  pause_request_en, pause_respect_en;
-   wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
-
-   wire [31:0] 	  debug_state;
-      
-   wire 	  tx_reset, rx_reset;
-   reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
-   reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
-   
-   simple_gemac simple_gemac
-     (.clk125(clk125),  .reset(reset),
-      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
-      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
-      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
-      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
-      .pause_req(pause_req), .pause_time_req(pause_time_req), 
-      .pause_respect_en(pause_respect_en),
-      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
-      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
-      .pass_pause(pass_pause), .pass_all(pass_all),
-      .rx_clk(rx_clk), .rx_data(rx_data),
-      .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
-      .tx_clk(tx_clk), .tx_data(tx_data), 
-      .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack),
-      .debug(debug_state)
-      );
-   
-   simple_gemac_wb simple_gemac_wb
-     (.wb_clk(wb_clk), .wb_rst(wb_rst),
-      .wb_cyc(wb_cyc), .wb_stb(wb_stb), .wb_ack(wb_ack), .wb_we(wb_we),
-      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
-      .mdio(mdio), .mdc(mdc),
-      .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
-      .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
-      .pass_pause(pass_pause), .pass_all(pass_all), 
-      .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
-      .pause_time(pause_time), .pause_thresh(pause_thresh) );
-
-   // RX FIFO Chain
-   wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
-   wire [7:0] 	  rx_ll_data;
-   
-   wire [18:0] 	  rx_f19_data_int1, rx_f19_data_int2;
-   wire 	  rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_src_rdy_int2, rx_f19_dst_rdy_int2;
-   
-   rxmac_to_ll8 rx_adapt
-     (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .rx_data(rx_data), .rx_valid(rx_valid), .rx_error(rx_error), .rx_ack(rx_ack),
-      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(),  // error also encoded in sof/eof
-      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy));
-
-   ll8_to_fifo19 ll8_to_fifo19
-     (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof),
-      .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy),
-      .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1));
-
-   fifo19_rxrealign fifo19_rxrealign
-     (.clk(rx_clk), .reset(rx_reset), .clear(0),
-      .datain(rx_f19_data_int1), .src_rdy_i(rx_f19_src_rdy_int1), .dst_rdy_o(rx_f19_dst_rdy_int1),
-      .dataout(rx_f19_data_int2), .src_rdy_o(rx_f19_src_rdy_int2), .dst_rdy_i(rx_f19_dst_rdy_int2) );
-
-   fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
-     (.wclk(rx_clk), .datain(rx_f19_data_int2), 
-      .src_rdy_i(rx_f19_src_rdy_int2), .dst_rdy_o(rx_f19_dst_rdy_int2), .space(rx_fifo_space),
-      .rclk(sys_clk), .dataout(rx_f19_data), 
-      .src_rdy_o(rx_f19_src_rdy), .dst_rdy_i(rx_f19_dst_rdy), .occupied(), .arst(reset));
-   
-   // TX FIFO Chain
-   wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
-   wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
-   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
-   wire [7:0] 	  tx_ll_data, tx_ll_data2;
-   wire [18:0] 	  tx_f19_data_int1;
-   wire 	  tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1;
-
-   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) tx_2clk_fifo
-     (.wclk(sys_clk), .datain(tx_f19_data), 
-      .src_rdy_i(tx_f19_src_rdy), .dst_rdy_o(tx_f19_dst_rdy), .space(),
-      .rclk(tx_clk), .dataout(tx_f19_data_int1), 
-      .src_rdy_o(tx_f19_src_rdy_int1), .dst_rdy_i(tx_f19_dst_rdy_int1), .occupied(), .arst(rx_reset));
-   
-   fifo19_to_ll8 fifo19_to_ll8
-     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
-      .f19_data(tx_f19_data_int1), .f19_src_rdy_i(tx_f19_src_rdy_int1), .f19_dst_rdy_o(tx_f19_dst_rdy_int1),
-      .ll_data(tx_ll_data2), .ll_sof_n(tx_ll_sof2_n), .ll_eof_n(tx_ll_eof2_n),
-      .ll_src_rdy_n(tx_ll_src_rdy2_n), .ll_dst_rdy_n(tx_ll_dst_rdy2_n));
-
-   assign tx_ll_sof2 	    = ~tx_ll_sof2_n;
-   assign tx_ll_eof2 	    = ~tx_ll_eof2_n;
-   assign tx_ll_src_rdy2    = ~tx_ll_src_rdy2_n;
-   assign tx_ll_dst_rdy2_n  = ~tx_ll_dst_rdy2;
-   
-   ll8_shortfifo tx_sfifo
-     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
-      .datain(tx_ll_data2), .sof_i(tx_ll_sof2), .eof_i(tx_ll_eof2),
-      .error_i(0), .src_rdy_i(tx_ll_src_rdy2), .dst_rdy_o(tx_ll_dst_rdy2),
-      .dataout(tx_ll_data), .sof_o(tx_ll_sof), .eof_o(tx_ll_eof),
-      .error_o(), .src_rdy_o(tx_ll_src_rdy), .dst_rdy_i(tx_ll_dst_rdy));
-   
-   ll8_to_txmac ll8_to_txmac
-     (.clk(tx_clk), .reset(tx_reset), .clear(clear),
-      .ll_data(tx_ll_data), .ll_sof(tx_ll_sof), .ll_eof(tx_ll_eof),
-      .ll_src_rdy(tx_ll_src_rdy), .ll_dst_rdy(tx_ll_dst_rdy),
-      .tx_data(tx_data), .tx_valid(tx_valid), .tx_error(tx_error), .tx_ack(tx_ack));
-
-   // Flow Control
-   flow_ctrl_rx flow_ctrl_rx
-     (.pause_request_en(pause_request_en), .pause_time(pause_time), .pause_thresh(pause_thresh),
-      .rx_clk(rx_clk), .rx_reset(rx_reset), .rx_fifo_space(rx_fifo_space),
-      .tx_clk(tx_clk), .tx_reset(tx_reset), .pause_req(pause_req), .pause_time_req(pause_time_req));
-   
-   wire [31:0] 	  debug_tx, debug_rx;
-
-   assign debug_tx  = { { tx_ll_data },
-			{ tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy, 
-			  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2 },
-			{ tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]},
-			{ tx_data} };
-   assign debug_rx  = { { rx_f19_src_rdy, rx_f19_dst_rdy, debug_state[5:0] },
-			{ rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 },
-			{ rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]},
-			{ rx_data} };
-
-   assign debug  = debug_rx;
-   
-endmodule // simple_gemac_wrapper19
diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v b/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
deleted file mode 100644
index 78f525fd7..000000000
--- a/usrp2/simple_gemac/simple_gemac_wrapper19_tb.v
+++ /dev/null
@@ -1,226 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-
-
-module simple_gemac_wrapper19_tb;
-`include "eth_tasks_f19.v"
-     
-   reg reset   = 1;
-   initial #1000 reset = 0;
-   wire wb_rst 	= reset;
-
-   reg eth_clk     = 0;
-   always #50 eth_clk = ~eth_clk;
-
-   reg wb_clk 	= 0;
-   always #173 wb_clk = ~wb_clk;
-
-   reg sys_clk 	= 0;
-   always #77 sys_clk = ~ sys_clk;
-   
-   wire GMII_RX_DV, GMII_RX_ER, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK;
-   wire [7:0] GMII_RXD, GMII_TXD;
-
-   wire rx_valid, rx_error, rx_ack;
-   wire tx_ack, tx_valid, tx_error;
-   
-   wire [7:0] rx_data, tx_data;
-   
-   reg [15:0] pause_time;
-   reg pause_req      = 0;
-
-   wire GMII_RX_CLK   = GMII_GTX_CLK;
-
-   reg [7:0] FORCE_DAT_ERR = 0;
-   reg FORCE_ERR = 0;
-   
-   // Loopback
-   assign GMII_RX_DV  = GMII_TX_EN;
-   assign GMII_RX_ER  = GMII_TX_ER | FORCE_ERR;
-   assign GMII_RXD    = GMII_TXD ^ FORCE_DAT_ERR;
-
-
-   wire [31:0] wb_dat_o;
-   reg [31:0]  wb_dat_i;
-   reg [7:0]   wb_adr;
-   reg 	       wb_stb=0, wb_cyc=0, wb_we=0;
-   wire        wb_ack;
-
-   reg [19:0]  tx_f19_data=0;
-   reg 	       tx_f19_src_rdy = 0;
-   wire        tx_f19_dst_rdy;
-   wire [35:0] rx_f19_data;
-   wire        rx_f19_src_rdy;
-   wire        rx_f19_dst_rdy = 1;
-   
-   simple_gemac_wrapper19 simple_gemac_wrapper19
-     (.clk125(eth_clk),  .reset(reset),
-      .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
-      .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
-      .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
-      .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
-      //.pause_req(pause_req), .pause_time(pause_time),
-
-      .sys_clk(sys_clk), .rx_f19_data(rx_f19_data), .rx_f19_src_rdy(rx_f19_src_rdy), .rx_f19_dst_rdy(rx_f19_dst_rdy),
-      .tx_f19_data(tx_f19_data), .tx_f19_src_rdy(tx_f19_src_rdy), .tx_f19_dst_rdy(tx_f19_dst_rdy),
-
-      .wb_clk(wb_clk), .wb_rst(wb_rst), .wb_stb(wb_stb), .wb_cyc(wb_cyc), .wb_ack(wb_ack), .wb_we(wb_we),
-      .wb_adr(wb_adr), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
-
-      .mdio(), .mdc(),
-      .debug() );
-   
-   initial $dumpfile("simple_gemac_wrapper19_tb.vcd");
-   initial $dumpvars(0,simple_gemac_wrapper19_tb);
-
-   integer i; 
-   reg [7:0] pkt_rom[0:65535];
-   reg [1023:0] ROMFile;
-   
-   initial
-     for (i=0;i<65536;i=i+1)
-       pkt_rom[i] <= 8'h0;
-
-   initial
-     begin
-	@(negedge reset);
-	repeat (10)
-	  @(posedge wb_clk);
-	WishboneWR(0,6'b111101); 
-	WishboneWR(4,16'hA0B0);
-	WishboneWR(8,32'hC0D0_A1B1);
-	WishboneWR(12,16'h0000);
-	WishboneWR(16,32'h0000_0000);
-	
-	@(posedge eth_clk);
-	SendFlowCtrl(16'h0007);  // Send flow control
-	@(posedge eth_clk);
-	#30000;
-	@(posedge eth_clk);
-	SendFlowCtrl(16'h0009);  // Increase flow control before it expires
-	#10000;
-	@(posedge eth_clk);
-	SendFlowCtrl(16'h0000);  // Cancel flow control before it expires
-	@(posedge eth_clk); 
-
-	repeat (1000)
-	  @(posedge sys_clk);
-	SendPacket_to_fifo19(32'hA0B0C0D0,10);    // This packet gets dropped by the filters
-	repeat (1000)
-	  @(posedge sys_clk);
-
-	SendPacket_to_fifo19(32'hAABBCCDD,100);    // This packet gets dropped by the filters
-	repeat (10)
-	  @(posedge sys_clk);
-/*
- 	SendPacketFromFile_f36(60,0,0);  // The rest are valid packets
-	repeat (10)
-	  @(posedge clk);
-
- 	SendPacketFromFile_f36(61,0,0);
-	repeat (10)
-	  @(posedge clk);
-	SendPacketFromFile_f36(62,0,0);
-	repeat (10)
-	  @(posedge clk);
-	SendPacketFromFile_f36(63,0,0);
-	repeat (1)
-	  @(posedge clk);
-	SendPacketFromFile_f36(64,0,0);
-	repeat (10)
-	  @(posedge clk);
-	SendPacketFromFile_f36(59,0,0);
-	repeat (1)
-	  @(posedge clk);
-	SendPacketFromFile_f36(58,0,0);
-	repeat (1)
-	  @(posedge clk);
-	SendPacketFromFile_f36(100,0,0);
-	repeat (1)
-	  @(posedge clk);
-	SendPacketFromFile_f36(200,150,30);  // waiting 14 empties the fifo, 15 underruns
-	repeat (1)
-	  @(posedge clk);
-	SendPacketFromFile_f36(100,0,30);
- */
-	#100000 $finish;
-     end
-
-   // Force a CRC error
-    initial
-     begin
-	#90000;
-	@(posedge eth_clk);
-	FORCE_DAT_ERR <= 8'h10;
-	@(posedge eth_clk);
-	FORCE_DAT_ERR <= 8'h00;
-     end
-
-   // Force an RX_ER error (i.e. link loss)
-   initial
-     begin
-	#116000;
-	@(posedge eth_clk);
-	FORCE_ERR <= 1;
-	@(posedge eth_clk);
-	FORCE_ERR <= 0;
-     end
-/*
-   // Cause receive fifo to fill, causing an RX overrun
-   initial
-     begin
-	#126000;
-	@(posedge clk);
-	rx_ll_dst_rdy2 <= 0;
-	repeat (30)          // Repeat of 14 fills the shortfifo, but works.  15 overflows
-	  @(posedge clk);
-	rx_ll_dst_rdy2 <= 1;
-     end
-  */
-   // Tests: Send and recv flow control, send and receive good packets, RX CRC err, RX_ER, RX overrun, TX underrun
-   // Still need to test: CRC errors on Pause Frames, MDIO, wishbone
-
-   task WishboneWR;
-      input [7:0] adr;
-      input [31:0] value;
-      begin
-	 wb_adr   <= adr;
-	 wb_dat_i <= value;
-	 wb_stb   <= 1;
-	 wb_cyc   <= 1;
-	 wb_we 	  <= 1;
-	 while (~wb_ack)
-	   @(posedge wb_clk);
-	 @(posedge wb_clk);
-	 wb_stb <= 0;
-	 wb_cyc <= 0;
-	 wb_we 	<= 0;
-      end
-   endtask // WishboneWR
-   /*
-   always @(posedge clk)
-     if(rx_ll_src_rdy2 & rx_ll_dst_rdy2)
-       begin
-	  if(rx_ll_sof2 & ~rx_ll_eof2)
-	    $display("RX-PKT-START %d",$time);
-	  $display("RX-PKT SOF %d EOF %d ERR%d DAT %x",rx_ll_sof2,rx_ll_eof2,rx_ll_error2,rx_ll_data2);
-	  if(rx_ll_eof2 & ~rx_ll_sof2)
-	    $display("RX-PKT-END %d",$time);
-       end
-   */
-endmodule // simple_gemac_wrapper19_tb