u2: redo the atr gpio pins, remove some old cruft

2 files changed, 48 insertions, 52 deletions

diff --git a/usrp2/control_lib/nsgpio.v b/usrp2/control_lib/nsgpio.v
index 26130cc8e..6c6873fee 100644
--- a/usrp2/control_lib/nsgpio.v
+++ b/usrp2/control_lib/nsgpio.v
@@ -37,71 +37,57 @@
 
 module nsgpio
   (input clk_i, input rst_i, 
-   input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] dat_i, 
+   input cyc_i, input stb_i, input [4:0] adr_i, input we_i, input [31:0] dat_i, 
    output reg [31:0] dat_o, output reg ack_o,
-   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
-   inout [31:0] gpio
+   input tx, input rx, inout [31:0] gpio
    );
 
-   reg [63:0] 	ctrl;
-   reg [31:0] 	line;
-   reg [31:0] 	lgpio;               // LatchedGPIO pins
-   reg [31:0] 	ddr;
+   integer n;
+   reg [31:0] ddr;
+   reg [31:0] idle_out, rx_out, tx_out, fdx_out;
+   reg [31:0] rgpio, igpio;
    
    wire 	wb_acc = cyc_i & stb_i;            // WISHBONE access
    wire 	wb_wr  = wb_acc & we_i;            // WISHBONE write access
 
    always @(posedge clk_i or posedge rst_i)
      if (rst_i)
-       begin
-          ctrl <= 64'h0;
-          line <= 0;
-       end
+       ddr <= 0;
      else if (wb_wr)
-       case( adr_i[3:2] )
-	 2'b00 : 
-           line <= dat_i;
-	 2'b01 :
-	   ddr[31:0] <= dat_i;
-	 2'b10 :
-	   ctrl[63:32] <= dat_i;
-	 2'b11 :
-	   ctrl[31:0] <= dat_i;
-       endcase // case( adr_i[3:2] )
-   
+       case( adr_i[4:2] )
+	 3'b000 : 
+           idle_out <= dat_i;
+	 3'b001 :
+	   rx_out <= dat_i;
+	 3'b010 :
+	   tx_out <= dat_i;
+	 3'b011 :
+	   fdx_out <= dat_i;
+	 3'b100 :
+	   ddr <= dat_i;
+       endcase // case ( adr_i[4:2] )
+      
    always @(posedge clk_i)
-     case (adr_i[3:2])
-       2'b00 :
-	 dat_o <= lgpio;
-       2'b01 :
-	 dat_o <= ddr;
-       2'b10 :
-	 dat_o <= ctrl[63:32];
-       2'b11 :
-	 dat_o <= ctrl[31:0];
-     endcase // case(adr_i[3:2])
+     dat_o <= gpio;
    
    always @(posedge clk_i or posedge rst_i)
      if (rst_i)
        ack_o <= 1'b0;
      else
        ack_o <= wb_acc & !ack_o;
-   
-   // latch GPIO input pins
+
    always @(posedge clk_i)
-     lgpio <= gpio;
-   
-   // assign GPIO outputs
-   integer   n;
-   reg [31:0] igpio; // temporary internal signal
+     case({tx,rx})
+       2'b00 : rgpio <= idle_out;
+       2'b01 : rgpio <= rx_out;
+       2'b10 : rgpio <= tx_out;
+       2'b11 : rgpio <= fdx_out;
+     endcase // case ({tx,rx})
    
-   always @(ctrl or line or debug_1 or debug_0 or atr or ddr)
+   always @*
      for(n=0;n<32;n=n+1)
-       igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : 
-			     (ctrl[2*n] ?  atr[n] : line[n]) )
-	 : 1'bz;
-   
+       igpio[n] <= ddr[n] ? rgpio[n] : 1'bz;
+
    assign     gpio = igpio;
    
 endmodule
-
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index a125e6b4c..0661de3c6 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -193,7 +193,7 @@ module u2_core
    wire 	uart_tx_int, uart_rx_int;
 
    wire [31:0] 	debug_gpio_0, debug_gpio_1;
-   wire [31:0] 	atr_lines;
+   //wire [31:0] 	atr_lines;
 
    wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
 		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo, debug_extfifo2;
@@ -423,12 +423,20 @@ module u2_core
    
    // /////////////////////////////////////////////////////////////////////////
    // GPIOs -- Slave #4
+
+   nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[4:0]),.we_i(s4_we),
+		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
+		 .tx(run_rx0_d1 | rx_rx1_d1), .rx(run_tx), .gpio({io_tx,io_rx}) );
+
+   /*
    nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
 		 .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
 		 .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
 		 .atr(atr_lines),.debug_0(debug_gpio_0),.debug_1(debug_gpio_1),
 		 .gpio({io_tx,io_rx}) );
-
+    */
    // /////////////////////////////////////////////////////////////////////////
    // Buffer Pool Status -- Slave #5   
    
@@ -539,12 +547,12 @@ module u2_core
    
    // /////////////////////////////////////////////////////////////////////////
    //  Simple Timer interrupts
-   
+   /*
    simple_timer #(.BASE(SR_SIMTIMER)) simple_timer
      (.clk(wb_clk), .reset(wb_rst),
       .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
       .onetime_int(onetime_int), .periodic_int(periodic_int));
-   
+   */
    // /////////////////////////////////////////////////////////////////////////
    // UART, Slave #10
 
@@ -558,11 +566,13 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // ATR Controller, Slave #11
 
+   /*
    atr_controller atr_controller
      (.clk_i(wb_clk),.rst_i(wb_rst),
       .adr_i(sb_adr[5:0]),.sel_i(sb_sel),.dat_i(sb_dat_o),.dat_o(sb_dat_i),
       .we_i(sb_we),.stb_i(sb_stb),.cyc_i(sb_cyc),.ack_o(sb_ack),
       .run_rx(run_rx0_d1 | run_rx1_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+   */
    
    // //////////////////////////////////////////////////////////////////////////
    // Time Sync, Slave #12 
@@ -572,16 +582,16 @@ module u2_core
    
    // /////////////////////////////////////////////////////////////////////////
    // SD Card Reader / Writer, Slave #13
-
+   /*
    sd_spi_wb sd_spi_wb
      (.clk(wb_clk),.rst(wb_rst),
       .sd_clk(sd_clk),.sd_csn(sd_csn),.sd_mosi(sd_mosi),.sd_miso(sd_miso),
       .wb_cyc_i(sd_cyc),.wb_stb_i(sd_stb),.wb_we_i(sd_we),
       .wb_adr_i(sd_adr[3:2]),.wb_dat_i(sd_dat_o[7:0]),.wb_dat_o(sd_dat_i[7:0]),
       .wb_ack_o(sd_ack) );
-
+    
    assign sd_dat_i[31:8] = 0;
-
+    */
    // /////////////////////////////////////////////////////////////////////////
    // ADC Frontend
    wire [23:0] 	 adc_i, adc_q;