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authorJosh Blum <josh@joshknows.com>2011-07-18 14:25:23 -0700
committerJosh Blum <josh@joshknows.com>2011-07-19 13:48:35 -0700
commit049376f205d560c98da779eee6903b8a8f71ebb5 (patch)
tree3e504254ea1425c07f7642fed94547d1eb581785 /usrp2
parentdd6d11c2255c646a48ff0c866b74c80869d94eac (diff)
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fpga: print timing report after generate bin file
Diffstat (limited to 'usrp2')
-rw-r--r--usrp2/top/Makefile.common5
-rwxr-xr-xusrp2/top/python/check_timing.py30
2 files changed, 34 insertions, 1 deletions
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
index 6f855a070..3a35e71e7 100644
--- a/usrp2/top/Makefile.common
+++ b/usrp2/top/Makefile.common
@@ -1,5 +1,5 @@
#
-# Copyright 2008, 2009, 2010 Ettus Research LLC
+# Copyright 2008-2011 Ettus Research LLC
#
##################################################
@@ -14,10 +14,12 @@ endif
BASE_DIR = $(abspath ..)
ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
SANITY_CHECKER = python $(BASE_DIR)/python/check_inout.py
+TIMING_CHECKER = python $(BASE_DIR)/python/check_timing.py
ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
BIT_FILE = $(BUILD_DIR)/$(TOP_MODULE).bit
MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs
+TWR_FILE = $(BUILD_DIR)/$(TOP_MODULE).twr
##################################################
# Global Targets
@@ -35,6 +37,7 @@ synth: $(ISE_FILE)
bin: check $(BIN_FILE)
$(ISE_HELPER) "Generate Programming File"
+ $(TIMING_CHECKER) $(TWR_FILE)
mcs: $(MCS_FILE)
diff --git a/usrp2/top/python/check_timing.py b/usrp2/top/python/check_timing.py
new file mode 100755
index 000000000..c57e889d0
--- /dev/null
+++ b/usrp2/top/python/check_timing.py
@@ -0,0 +1,30 @@
+#!/usr/bin/env python
+#
+# Copyright 2011 Ettus Research LLC
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+import sys
+import re
+
+def print_timing_constraint_summary(twr_file):
+ output = ""
+ keep = False
+ for line in open(twr_file).readlines():
+ if 'Derived Constraint Report' in line: keep = True
+ if keep: output += line
+ if 'constraint' in line and 'met' in line: break
+ print("\n\n"+output)
+
+if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:])