dsp rework: custom engine module for rx/tx vita chain

2 files changed, 35 insertions, 35 deletions

diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index 150da31c9..bd416f563 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -20,9 +20,11 @@ module vita_rx_chain
   #(parameter BASE=0,
     parameter UNIT=0,
     parameter FIFOSIZE=10,
-    parameter PROT_ENG_FLAGS=1)
+    parameter PROT_ENG_FLAGS=1,
+    parameter DSP_NUMBER=0)
    (input clk, input reset,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
     input [63:0] vita_time,
     input [31:0] sample, input strobe,
     output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i,
@@ -72,9 +74,10 @@ module vita_rx_chain
       .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int),
       .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2));
 
-   dspengine_16to8 #(.BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_16to8
-     (.clk(clk),.reset(reset),.clear(clear),
-      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+   custom_engine_rx #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_rx
+     (.clock(clk),.reset(reset),.clear(clear),
+      .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data),
+      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), 
       .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), 
       .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 61df19097..78f63b555 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -19,7 +19,6 @@
 module vita_tx_chain
   #(parameter BASE=0,
     parameter FIFOSIZE=10,
-    parameter POST_ENGINE_FIFOSIZE=0,
     parameter REPORT_ERROR=0,
     parameter DO_FLOW_CONTROL=0,
     parameter PROT_ENG_FLAGS=0,
@@ -27,6 +26,7 @@ module vita_tx_chain
     parameter DSP_NUMBER=0)
    (input clk, input reset,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
     input [63:0] vita_time,
     input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
     output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
@@ -62,39 +62,36 @@ module vita_tx_chain
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(streamid),.changed(clear_seqnum));
 
-   wire [FIFOSIZE-1:0] access_adr, access_len;
-   wire 	       access_we, access_stb, access_ok, access_done, access_skip_read;
-   wire [35:0] 	       dsp_to_buf, buf_to_dsp;
-   wire [35:0] 	       tx_data_int1, tx_data_int2;
-   wire 	       tx_src_rdy_int1, tx_dst_rdy_int1, tx_src_rdy_int2, tx_dst_rdy_int2;
-
-   double_buffer #(.BUF_SIZE(FIFOSIZE)) db
-     (.clk(clk),.reset(reset),.clear(clear),
-      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
-      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
-      .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),
-
-      .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
-      .data_o(tx_data_int1), .src_rdy_o(tx_src_rdy_int1), .dst_rdy_i(tx_dst_rdy_int1));
-
-   dspengine_8to16 #(.BASE(BASE+6), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_8to16
-     (.clk(clk),.reset(reset),.clear(clear),
-      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
-      .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
-      .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
+   wire [35:0] tx_data_int1;
+   wire tx_src_rdy_int1, tx_dst_rdy_int1;
 
     generate
-    if (POST_ENGINE_FIFOSIZE==0) begin
-        assign tx_data_int2 = tx_data_int1;
-        assign tx_src_rdy_int2 = tx_src_rdy_int1;
-        assign tx_dst_rdy_int1 = tx_dst_rdy_int2;
+    if (FIFOSIZE==0) begin
+        assign tx_data_int1 = tx_data_i;
+        assign tx_src_rdy_int1 = tx_src_rdy_i;
+        assign tx_dst_rdy_o = tx_dst_rdy_int1;
     end
     else begin
-       fifo_cascade #(.WIDTH(36), .SIZE(POST_ENGINE_FIFOSIZE)) post_engine_buffering(
-        .clk(clk), .reset(reset), .clear(clear),
-        .datain(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1),
-        .dataout(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2));
+       wire [FIFOSIZE-1:0] access_adr, access_len;
+       wire 	       access_we, access_stb, access_ok, access_done, access_skip_read;
+       wire [35:0] 	       dsp_to_buf, buf_to_dsp;
+
+       double_buffer #(.BUF_SIZE(FIFOSIZE)) db
+         (.clk(clk),.reset(reset),.clear(clear),
+          .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
+          .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
+          .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp),
+
+          .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
+          .data_o(tx_data_int1), .src_rdy_o(tx_src_rdy_int1), .dst_rdy_i(tx_dst_rdy_int1));
+
+       custom_engine_tx #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+6), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_tx
+         (.clock(clk),.reset(reset),.clear(clear),
+          .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data),
+          .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+          .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),
+          .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
+          .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
     end
     endgenerate
 
@@ -104,7 +101,7 @@ module vita_tx_chain
    vita_tx_deframer
      (.clk(clk), .reset(reset), .clear(clear), .clear_seqnum(clear_seqnum),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .data_i(tx_data_int2), .src_rdy_i(tx_src_rdy_int2), .dst_rdy_o(tx_dst_rdy_int2),
+      .data_i(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1),
       .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
       .current_seqnum(current_seqnum),
       .debug(debug_vtd) );