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authorJosh Blum <josh@joshknows.com>2012-04-09 19:53:51 -0700
committerJosh Blum <josh@joshknows.com>2012-04-09 19:53:51 -0700
commit510632d8968eb95d383da4cf2d72184d66da0bee (patch)
treea2b49b87c7965854d3a7d56ae78738228ed6e1e7 /usrp2/vrt
parenta40bb6e9b79f1ad519848dff6054d32a1cda2380 (diff)
parentbcca51705e82b247175d4d9563ad9d7b35b51750 (diff)
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Merge branch 'master' into next
Conflicts: usrp2/top/N2x0/u2plus_core.v usrp2/top/USRP2/u2_core.v
Diffstat (limited to 'usrp2/vrt')
-rw-r--r--usrp2/vrt/vita_rx_chain.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index ca2f847bc..2788dc9d5 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -41,7 +41,7 @@ module vita_rx_chain
wire clear;
assign clear_o = clear;
wire clear_int;
- setting_reg #(.my_addr(BASE+3)) sr
+ setting_reg #(.my_addr(BASE+8)) sr
(.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(),.changed(clear_int));