dsp rework: pass vita clears into dsp modules, unified fifo clears

2 files changed, 5 insertions, 5 deletions

diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index e4f7e9864..c57e6cc05 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -28,9 +28,9 @@ module vita_rx_chain
     input [63:0] vita_time,
     input [31:0] sample, input strobe,
     output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i,
-    output overrun, output run,
+    output overrun, output run, output clear_o,
     output [31:0] debug );
-       
+
    wire [100:0] sample_data;
    wire 	sample_dst_rdy, sample_src_rdy;
    wire [31:0] 	vrc_debug, vrf_debug;
@@ -39,6 +39,7 @@ module vita_rx_chain
    wire 	rx_src_rdy_int, rx_dst_rdy_int;
 
    wire clear;
+   assign clear_o = clear;
 
    setting_reg #(.my_addr(BASE+3)) sr
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 93bc703cd..9b478081f 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -32,8 +32,7 @@ module vita_tx_chain
     input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
     output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
     output [31:0] sample, input strobe,
-    output underrun, output run,
-    output clear_vita,
+    output underrun, output run, output clear_o,
     output [31:0] debug);
 
    localparam MAXCHAN = 1;
@@ -51,7 +50,7 @@ module vita_tx_chain
    wire [31:0] 		current_seqnum;
 
    wire clear;
-   assign clear_vita = clear;
+   assign clear_o = clear;
    assign underrun = error;
    assign message = error_code;