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| author | Matt Ettus <matt@ettus.com> | 2011-10-06 22:56:51 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-10-26 15:57:22 -0700 |
| commit | 80ec54d3f39536461c09c960c296e7c02c418310 (patch) | |
| tree | 816eb661f0a4b1287877d30dd5c9cae97e055a74 /usrp2/vrt | |
| parent | f4c61186f6a81a09a038cef500d07d4ca5e65a57 (diff) | |
| download | uhd-80ec54d3f39536461c09c960c296e7c02c418310.tar.gz uhd-80ec54d3f39536461c09c960c296e7c02c418310.tar.bz2 uhd-80ec54d3f39536461c09c960c296e7c02c418310.zip | |
dspengine: insert into the rx chain
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index 1986743b3..28b5ea9ff 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -50,11 +50,33 @@ module vita_rx_chain .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .debug_rx(vrf_debug) ); + wire [FIFOSIZE-1:0] access_adr, access_len; + wire access_we, access_stb, access_ok, access_done, access_skip_read; + wire [35:0] dsp_to_buf, buf_to_dsp; + wire [35:0] rx_data_int2; + wire rx_src_rdy_int2, rx_dst_rdy_int2; + + double_buffer #(.BUF_SIZE(FIFOSIZE)) db + (.clk(clk),.reset(reset),.clear(clear), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(dsp_to_buf), .access_dat_o(buf_to_dsp), + + .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), + .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2)); + + dspengine_16to8 #(.BASE(BASE+3), .BUF_SIZE(FIFOSIZE)) dspengine_16to8 + (.clk(clk),.reset(rst),.clear(clear), + .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), + .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), + .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); + dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT), .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp0_framer36 (.clk(clk), .reset(reset), .clear(clear), - .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), + .data_i(rx_data_int2), .src_rdy_i(rx_src_rdy_int2), .dst_rdy_o(rx_dst_rdy_int2), .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); assign debug = vrc_debug; // | vrf_debug; |