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| author | Josh Blum <josh@joshknows.com> | 2012-02-10 12:13:51 -0800 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-02-10 12:13:51 -0800 |
| commit | 6d45600ada785cb50a01a17dcddf561d12501d22 (patch) | |
| tree | c223f87aebf64f305b4bfe83e0ce799d01dad59a /usrp2/vrt | |
| parent | 34db74740704ce2de2a71447b3d202e9c4be800b (diff) | |
| download | uhd-6d45600ada785cb50a01a17dcddf561d12501d22.tar.gz uhd-6d45600ada785cb50a01a17dcddf561d12501d22.tar.bz2 uhd-6d45600ada785cb50a01a17dcddf561d12501d22.zip | |
dsp rework: pass enables into glue, update power trig, parameterize, fix module inc
DSP enables now pass through the glue and custom modules so it can be user-controlled.
Updated power trigger to current spec, and added comments
Pass width from dsp into glue, and use width to parameterize wires
Fix custom module includes so they will build
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/vita_rx_engine_glue.v | 4 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_engine_glue.v | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/usrp2/vrt/vita_rx_engine_glue.v b/usrp2/vrt/vita_rx_engine_glue.v index 86e3d1114..56447a7aa 100644 --- a/usrp2/vrt/vita_rx_engine_glue.v +++ b/usrp2/vrt/vita_rx_engine_glue.v @@ -65,7 +65,7 @@ module vita_rx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom + `RX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng0_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), @@ -82,7 +82,7 @@ module vita_rx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom + `RX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE)) rx_eng1_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), diff --git a/usrp2/vrt/vita_tx_engine_glue.v b/usrp2/vrt/vita_tx_engine_glue.v index b0a81c3e9..db0d55dee 100644 --- a/usrp2/vrt/vita_tx_engine_glue.v +++ b/usrp2/vrt/vita_tx_engine_glue.v @@ -69,7 +69,7 @@ module vita_tx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng0_custom + `TX_ENG0_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng0_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), @@ -86,7 +86,7 @@ module vita_tx_engine_glue .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(access_dat_i), .access_dat_o(access_dat_o)); `else - TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng1_custom + `TX_ENG1_MODULE #(.BUF_SIZE(BUF_SIZE), .HEADER_OFFSET(HEADER_OFFSET)) tx_eng1_custom (.clock(clock),.reset(reset),.clear(clear), .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), |