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| author | Matt Ettus <matt@ettus.com> | 2011-10-12 15:20:48 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-10-26 15:57:22 -0700 |
| commit | 406345b14c745c0c3e7ac7c47ce6e893c61e357e (patch) | |
| tree | 75c215a345b7366ef17ddb1e0b8ac3c88e3afb92 /usrp2/vrt | |
| parent | 550e32bd1ef550a7b90e9aec4baa6a10fb247176 (diff) | |
| download | uhd-406345b14c745c0c3e7ac7c47ce6e893c61e357e.tar.gz uhd-406345b14c745c0c3e7ac7c47ce6e893c61e357e.tar.bz2 uhd-406345b14c745c0c3e7ac7c47ce6e893c61e357e.zip | |
dsp_engine fix rst -> reset, default to read address
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index 14c454f8a..63e1e45dd 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -66,7 +66,7 @@ module vita_rx_chain .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2)); dspengine_16to8 #(.BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_16to8 - (.clk(clk),.reset(rst),.clear(clear), + (.clk(clk),.reset(reset),.clear(clear), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), |