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authorJosh Blum <josh@joshknows.com>2012-01-30 22:22:56 -0800
committerJosh Blum <josh@joshknows.com>2012-01-30 22:22:56 -0800
commit327c25864e3d09fdc34fe9f438dded1329b0c65c (patch)
tree5b6c7b28f1ad20c091d52da156642c5790d39d3d /usrp2/vrt
parent9803334f95c548b7fdf9a9d73c41e6e22f252dcb (diff)
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dsp rework: work on 8 to 16 engine (usrp2 ok)
Diffstat (limited to 'usrp2/vrt')
-rw-r--r--usrp2/vrt/vita_tx_chain.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index f9348bbfd..8002eae83 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -76,7 +76,7 @@ module vita_tx_chain
.data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
.data_o(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2));
- dspengine_8to16 #(.BASE(BASE+6), .BUF_SIZE(FIFOSIZE)) dspengine_8to16
+ dspengine_8to16 #(.BASE(BASE+6), .BUF_SIZE(FIFOSIZE), .HEADER_OFFSET(USE_TRANS_HEADER)) dspengine_8to16
(.clk(clk),.reset(reset),.clear(clear),
.set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
.access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done),