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| author | Matt Ettus <matt@ettus.com> | 2011-07-28 12:08:23 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-07-28 12:08:23 -0700 |
| commit | 16f33c73b3a3303d183ebaabcb5fe968bb31c4e8 (patch) | |
| tree | 4510a63d506a338344c67c792fd7cee4e7883f22 /usrp2/vrt | |
| parent | 003664fe4e74d6c80cea1c6b06cbd1d1233377f6 (diff) | |
| download | uhd-16f33c73b3a3303d183ebaabcb5fe968bb31c4e8.tar.gz uhd-16f33c73b3a3303d183ebaabcb5fe968bb31c4e8.tar.bz2 uhd-16f33c73b3a3303d183ebaabcb5fe968bb31c4e8.zip | |
vrt: delay the late signal to help with timing
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/vita_rx_control.v | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index b6b55d9d0..daec734a8 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -121,10 +121,19 @@ module vita_rx_control time_compare time_compare (.time_now(vita_time), .trigger_time(rcvtime), .now(now), .early(early), .late(late)); - wire too_late = late & ~send_imm; wire go_now = now | send_imm; wire full = ~sample_fifo_in_rdy; + reg too_late; + + always @(posedge clk) + if(reset | clear) + too_late <= 0; + else + too_late <= late & ~send_imm; + + reg late_valid; + always @(posedge clk) if(reset | clear) begin @@ -135,6 +144,7 @@ module vita_rx_control send_imm <= 0; chain <= 0; reload <= 0; + late_valid <= 0; end else case(ibs_state) @@ -144,6 +154,7 @@ module vita_rx_control lines_left <= numlines_pre; lines_total <= numlines_pre; rcvtime <= rcvtime_pre; + late_valid <= 0; if(stop_pre) ibs_state <= IBS_ZEROLEN; else @@ -153,10 +164,14 @@ module vita_rx_control reload <= reload_pre; end IBS_WAITING : - if(go_now) - ibs_state <= IBS_RUNNING; - else if(too_late) - ibs_state <= IBS_LATECMD; + begin + late_valid <= 1; + if(late_valid) + if(go_now) + ibs_state <= IBS_RUNNING; + else if(too_late) + ibs_state <= IBS_LATECMD; + end IBS_RUNNING : if(strobe) if(full) |