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| author | Matt Ettus <matt@ettus.com> | 2010-12-15 17:37:58 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-12-15 17:37:58 -0800 |
| commit | 54588404b0e168d42ca963a282c61fa137612a63 (patch) | |
| tree | e538beb9b00e971dc746e37908e8cd2e708e34a5 /usrp2/vrt | |
| parent | 21c3765da33652ec186e230d2aabc52625e32d7f (diff) | |
| download | uhd-54588404b0e168d42ca963a282c61fa137612a63.tar.gz uhd-54588404b0e168d42ca963a282c61fa137612a63.tar.bz2 uhd-54588404b0e168d42ca963a282c61fa137612a63.zip | |
generate port number headers in the dsp error units
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/gen_context_pkt.v | 7 | ||||
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 7 |
2 files changed, 8 insertions, 6 deletions
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v index 44bb7b548..cc34cceed 100644 --- a/usrp2/vrt/gen_context_pkt.v +++ b/usrp2/vrt/gen_context_pkt.v @@ -1,7 +1,8 @@ module gen_context_pkt - #(parameter PROT_ENG_FLAGS=1) + #(parameter PROT_ENG_FLAGS=1, + parameter DSP_NUMBER=0) (input clk, input reset, input clear, input trigger, output sent, input [31:0] streamid, @@ -67,10 +68,10 @@ module gen_context_pkt endcase // case (ctxt_state) assign src_rdy_int = ~( (ctxt_state == CTXT_IDLE) | (ctxt_state == CTXT_DONE) ); - + always @* case(ctxt_state) - CTXT_PROT_ENG : data_int <= { 2'b01, 16'd1, 16'd28 }; + CTXT_PROT_ENG : data_int <= { 2'b01, 13'b0, DSP_NUMBER[0], 1'b1, 1'b1, 16'd28 }; // UDP port 1 or 3 CTXT_HEADER : data_int <= { 1'b0, (PROT_ENG_FLAGS ? 1'b0 : 1'b1), 12'b010100001101, seqno, 16'd7 }; CTXT_STREAMID : data_int <= { 2'b00, streamid }; CTXT_SECS : data_int <= { 2'b00, err_time[63:32] }; diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 2ec78189b..6f567668d 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -5,7 +5,8 @@ module vita_tx_chain parameter REPORT_ERROR=0, parameter DO_FLOW_CONTROL=0, parameter PROT_ENG_FLAGS=0, - parameter USE_TRANS_HEADER=0) + parameter USE_TRANS_HEADER=0, + parameter DSP_NUMBER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, @@ -71,7 +72,7 @@ module vita_tx_chain wire [35:0] flow_data, err_data_int; wire flow_src_rdy, flow_dst_rdy, err_src_rdy_int, err_dst_rdy_int; - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_flow_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_flow_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger(trigger & (DO_FLOW_CONTROL==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(32'd0), @@ -82,7 +83,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .packet_consumed(packet_consumed), .trigger(trigger)); - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS),.DSP_NUMBER(DSP_NUMBER)) gen_tx_err_pkt (.clk(clk), .reset(reset), .clear(clear_vita), .trigger((error|ack) & (REPORT_ERROR==1)), .sent(), .streamid(streamid), .vita_time(vita_time), .message(message), |