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authorJosh Blum <josh@joshknows.com>2012-02-01 09:47:07 -0800
committerJosh Blum <josh@joshknows.com>2012-02-01 09:47:07 -0800
commitc407516349601831767952a9b12a077a2f23ea51 (patch)
tree5733a0bf569d354dad9890b0a2fc024856ad5df5 /usrp2/vrt
parent7b69532aca8cc44017dedc1bfb07fa0d27b8ea6d (diff)
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dsp rework: paramaterize post_engine_buffering
Diffstat (limited to 'usrp2/vrt')
-rw-r--r--usrp2/vrt/vita_tx_chain.v18
1 files changed, 14 insertions, 4 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 189876015..61df19097 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -19,6 +19,7 @@
module vita_tx_chain
#(parameter BASE=0,
parameter FIFOSIZE=10,
+ parameter POST_ENGINE_FIFOSIZE=0,
parameter REPORT_ERROR=0,
parameter DO_FLOW_CONTROL=0,
parameter PROT_ENG_FLAGS=0,
@@ -83,10 +84,19 @@ module vita_tx_chain
.access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len),
.access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf));
- fifo_cascade #(.WIDTH(36), .SIZE(9)) post_engine_buffering(
- .clk(clk), .reset(reset), .clear(clear),
- .datain(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1),
- .dataout(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2));
+ generate
+ if (POST_ENGINE_FIFOSIZE==0) begin
+ assign tx_data_int2 = tx_data_int1;
+ assign tx_src_rdy_int2 = tx_src_rdy_int1;
+ assign tx_dst_rdy_int1 = tx_dst_rdy_int2;
+ end
+ else begin
+ fifo_cascade #(.WIDTH(36), .SIZE(POST_ENGINE_FIFOSIZE)) post_engine_buffering(
+ .clk(clk), .reset(reset), .clear(clear),
+ .datain(tx_data_int1), .src_rdy_i(tx_src_rdy_int1), .dst_rdy_o(tx_dst_rdy_int1),
+ .dataout(tx_data_int2), .src_rdy_o(tx_src_rdy_int2), .dst_rdy_i(tx_dst_rdy_int2));
+ end
+ endgenerate
vita_tx_deframer #(.BASE(BASE),
.MAXCHAN(MAXCHAN),