tx error packets now muxed into the ethernet stream back to the host

3 files changed, 44 insertions, 20 deletions

diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs
index 07c62224b..dc4bd8c96 100644
--- a/usrp2/vrt/Makefile.srcs
+++ b/usrp2/vrt/Makefile.srcs
@@ -10,4 +10,6 @@ vita_rx_control.v \
 vita_rx_framer.v \
 vita_tx_control.v \
 vita_tx_deframer.v \
+vita_tx_chain.v \
+gen_context_pkt.v \
 ))
diff --git a/usrp2/vrt/gen_context_pkt.v b/usrp2/vrt/gen_context_pkt.v
index 9e3fcbca8..2fad43cc6 100644
--- a/usrp2/vrt/gen_context_pkt.v
+++ b/usrp2/vrt/gen_context_pkt.v
@@ -1,7 +1,7 @@
 
 
 module gen_context_pkt
-  #(parameter PROT_ENG_FLAGS =1)
+  #(parameter PROT_ENG_FLAGS=1)
    (input clk, input reset, input clear,
     input trigger, output sent,
     input [31:0] streamid,
@@ -23,6 +23,7 @@ module gen_context_pkt
    wire 	 src_rdy_int, dst_rdy_int;
    wire [3:0] 	 seqno = 0;
    reg [3:0] 	 ctxt_state;
+   reg [63:0] 	 err_time;
    
    always @(posedge clk)
      if(reset | clear)
@@ -31,7 +32,10 @@ module gen_context_pkt
        case(ctxt_state)
 	 CTXT_IDLE :
 	   if(trigger)
-	     ctxt_state <= CTXT_HEADER;
+	     begin
+		ctxt_state <= CTXT_HEADER;
+		err_time <= vita_time;
+	     end
 	 
 	 CTXT_DONE :
 	   if(~trigger)
@@ -48,9 +52,9 @@ module gen_context_pkt
      case(ctxt_state)
        CTXT_HEADER : data_int <= { 2'b01, 12'b010100001101, seqno, 16'd6 };
        CTXT_STREAMID : data_int <= { 2'b00, streamid };
-       CTXT_SECS : data_int <= { 2'b00, vita_time[63:32] };
+       CTXT_SECS : data_int <= { 2'b00, err_time[63:32] };
        CTXT_TICS : data_int <= { 2'b00, 32'd0 };
-       CTXT_TICS2 : data_int <= { 2'b00, vita_time[31:0] };
+       CTXT_TICS2 : data_int <= { 2'b00, err_time[31:0] };
        CTXT_MESSAGE : data_int <= { 2'b10, message };
        default : {2'b00, 32'b00};
      endcase // case (ctxt_state)
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 17cfe1799..66f775ddf 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -1,13 +1,16 @@
 
 module vita_tx_chain
-  #(parameter SR_TX_CTRL=0,
-    parameter SR_TX_DSP=0)
-   (input dsp_clk, input dsp_rst,
-    input set_stb_dsp, input [7:0] set_addr_dsp, input [31:0] set_data_dsp,
+  #(parameter BASE_CTRL=0,
+    parameter BASE_DSP=0,
+    parameter REPORT_ERROR=0,
+    parameter PROT_ENG_FLAGS=0)
+   (input clk, input reset,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
     input [63:0] vita_time,
     input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
+    input [35:0] err_data_i, input err_src_rdy_i, output err_dst_rdy_o,
     output [15:0] dac_a, output [15:0] dac_b,
-    output underrun, output run_tx,
+    output underrun, output run,
     output [31:0] debug);
    
    wire [31:0] 	  debug_vtc, debug_vtd, debug_tx_dsp;
@@ -15,29 +18,44 @@ module vita_tx_chain
    wire 	  tx1_src_rdy, tx1_dst_rdy;
    wire 	  clear_vita;
    wire [31:0] 	  sample_tx;
+   wire [31:0] 	  streamid, message;
+   wire 	  trigger, sent;
    
-   vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita),
-      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+   setting_reg #(.my_addr(BASE_CTRL+1), .at_reset(0)) sr_streamid
+     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(streamid),.changed());
+
+   vita_tx_deframer #(.BASE(BASE_CTRL), .MAXCHAN(1)) vita_tx_deframer
+     (.clk(clk), .reset(reset), .clear(clear_vita),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
       .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
       .debug(debug_vtd) );
 
-   vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita),
-      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+   vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32)) vita_tx_control
+     (.clk(clk), .reset(reset), .clear(clear_vita),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .vita_time(vita_time),.underrun(underrun),
       .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
-      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .sample(sample_tx), .run(run), .strobe(strobe_tx),
       .debug(debug_vtc) );
    
-   dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
-     (.clk(dsp_clk),.rst(dsp_rst),
-      .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
-      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+   dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx
+     (.clk(clk),.rst(reset),
+      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .sample(sample_tx), .run(run), .strobe(strobe_tx),
       .dac_a(dac_a),.dac_b(dac_b),
       .debug(debug_tx_dsp) );
 
+   generate
+      if(REPORT_ERROR==1)
+	gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt
+	  (.clk(clk), .reset(reset), .clear(clear_vita),
+	   .trigger(underrun), .sent(), 
+	   .streamid(streamid), .vita_time(vita_time), .message(message),
+	   .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i));
+   endgenerate
+   
    assign debug = debug_vtc | debug_vtd;
    
 endmodule // vita_tx_chain