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author | Josh Blum <josh@joshknows.com> | 2012-04-09 19:51:38 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2012-04-09 19:51:38 -0700 |
commit | bcca51705e82b247175d4d9563ad9d7b35b51750 (patch) | |
tree | 91d6a6fb5f2035453c3ffea2af74ed059487c518 /usrp2/vrt | |
parent | 91f0498372e36d47eccb26cf42118e749cfd6251 (diff) | |
parent | f136b06211dc0fe572d77219b6ce579963d435fe (diff) | |
download | uhd-bcca51705e82b247175d4d9563ad9d7b35b51750.tar.gz uhd-bcca51705e82b247175d4d9563ad9d7b35b51750.tar.bz2 uhd-bcca51705e82b247175d4d9563ad9d7b35b51750.zip |
Merge branch 'maint'
Diffstat (limited to 'usrp2/vrt')
-rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index ca2f847bc..2788dc9d5 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -41,7 +41,7 @@ module vita_rx_chain wire clear; assign clear_o = clear; wire clear_int; - setting_reg #(.my_addr(BASE+3)) sr + setting_reg #(.my_addr(BASE+8)) sr (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_int)); |