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| author | Matt Ettus <matt@ettus.com> | 2011-03-25 15:55:50 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
| commit | 9fe534886ce3515b08aca53cae5dff336e53147e (patch) | |
| tree | e42d66fedc8c1869e643646db212e0f8f671af3e /usrp2/vrt | |
| parent | b8f5df998505727321cd23d04d23a89fd616cb9c (diff) | |
| download | uhd-9fe534886ce3515b08aca53cae5dff336e53147e.tar.gz uhd-9fe534886ce3515b08aca53cae5dff336e53147e.tar.bz2 uhd-9fe534886ce3515b08aca53cae5dff336e53147e.zip | |
u1p: debug pins
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/vita_rx_control.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 4c0cef50d..73d9b87fd 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -191,9 +191,9 @@ module vita_rx_control assign read_ctrl = ( (ibs_state == IBS_IDLE) | ((ibs_state == IBS_RUNNING) & strobe & ~full & (lines_left==1) & chain) ) & not_empty_ctrl; - assign debug_rx = { { ibs_state[2:0], command_queue_len }, + assign debug_rx = { { 8'd0 }, { 8'd0 }, - { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, ~not_empty_ctrl }, - { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; + { go_now, too_late, run, strobe, read_ctrl, write_ctrl, overrun, ~not_empty_ctrl }, + { ibs_state[2:0], chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} }; endmodule // vita_rx_control |