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| author | Matt Ettus <matt@ettus.com> | 2011-05-09 14:58:30 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-05-09 14:58:30 -0700 |
| commit | d8aae182ffdafdd61bbd0100f845d7c93e6ec591 (patch) | |
| tree | 356eba18476f8165367a9bc3585c9df9b44680e1 /usrp2/vrt | |
| parent | d5a97d111b9f7baeee0fb9f2e1efbad9a16a83d4 (diff) | |
| download | uhd-d8aae182ffdafdd61bbd0100f845d7c93e6ec591.tar.gz uhd-d8aae182ffdafdd61bbd0100f845d7c93e6ec591.tar.bz2 uhd-d8aae182ffdafdd61bbd0100f845d7c93e6ec591.zip | |
u1e: get dsp_framer36 from u1p so it can skip the protocol header
Diffstat (limited to 'usrp2/vrt')
| -rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index d7498286d..28955d108 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -2,7 +2,8 @@ module vita_rx_chain #(parameter BASE=0, parameter UNIT=0, - parameter FIFOSIZE=10) + parameter FIFOSIZE=10, + parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, output overrun, @@ -15,7 +16,7 @@ module vita_rx_chain wire [31:0] vrc_debug, vrf_debug; wire [35:0] rx_data_int; - wire rx_src_rdy_int, rx_dst_rdy_in; + wire rx_src_rdy_int, rx_dst_rdy_int; vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), @@ -32,7 +33,9 @@ module vita_rx_chain .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .debug_rx(vrf_debug) ); - dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36 + dsp_framer36 #(.BUF_SIZE(FIFOSIZE), + .PORT_SEL(UNIT), + .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp0_framer36 (.clk(clk), .reset(reset), .clear(clear), .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); |