Merge branch 'tx_policy' into u2p_txpolicy

* tx_policy: (21 commits)
  clean up DAC inversion and swapping to match schematics
  Clean up iq swapping on RX.  It is now swapped in the top level. widened muxes to 4 bits to match tx side and handle more ADCs in future
  rx error context packets should not be marked as errors in the fifo
  added compat number to usrp2 readback mux
  makefile dependency fix for second expansion
  provide a way to get out of the error state without processor intervention
  sequence number reset upon programming streamid
  attempt at avoiding infinite error messages
  implemented "next packet" and "next burst" policies
  sequence errors can happen on start of burst as well.
  more informative error codes
  cleaner error handling
  introduce new error types
  test mux and gen_context_pkt
  this is an output file, it shouldn't be checked in
  insert protocol engine flags when requested
  move the streamid so it isn't at the same address as clear_state
  connect the demux
  fix a typo
  tx error packets now muxed into the ethernet stream back to the host
  ...

1 files changed, 23 insertions, 7 deletions

diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 3b95f5902..f9cd7d00d 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -2,7 +2,7 @@
 module vita_tx_deframer
   #(parameter BASE=0,
     parameter MAXCHAN=1)
-   (input clk, input reset, input clear,
+   (input clk, input reset, input clear, input clear_seqnum,
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
     
     // To FIFO interface of Buffer Pool
@@ -10,7 +10,7 @@ module vita_tx_deframer
     input src_rdy_i,
     output dst_rdy_o,
     
-    output [4+64+(32*MAXCHAN)-1:0] sample_fifo_o,
+    output [5+64+16+(32*MAXCHAN)-1:0] sample_fifo_o,
     output sample_fifo_src_rdy_o,
     input sample_fifo_dst_rdy_i,
     
@@ -21,6 +21,8 @@ module vita_tx_deframer
     output [31:0] debug
     );
 
+   localparam FIFOWIDTH = 5+64+16+(32*MAXCHAN);
+   
    wire [1:0] numchan;
    setting_reg #(.my_addr(BASE), .at_reset(0), .width(2)) sr_numchan
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
@@ -36,14 +38,18 @@ module vita_tx_deframer
    assign is_sob = data_i[25];
    assign is_eob = data_i[24];
    wire      eof = data_i[33];
-   
    reg 	     has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg;
    reg 	     has_trailer_reg, is_sob_reg, is_eob_reg;
-
+   
    reg [15:0] pkt_len;
    reg [1:0]  vector_phase;
    wire       line_done;
    
+   reg 	      seqnum_err;
+   reg [3:0]  seqnum_reg;
+   wire [3:0] seqnum = data_i[19:16];
+   wire [3:0] next_seqnum = seqnum_reg + 4'd1;
+   
    // Output FIFO for packetized data
    localparam VITA_HEADER 	 = 0;
    localparam VITA_STREAMID 	 = 1;
@@ -61,6 +67,13 @@ module vita_tx_deframer
 
    wire        eop = eof | (pkt_len==hdr_len);  // FIXME would ignoring eof allow larger VITA packets?
    wire        fifo_space;
+
+   always @(posedge clk)
+     if(reset | clear_seqnum)
+       seqnum_reg <= 4'hF;
+     else
+       if((vita_state==VITA_HEADER) & src_rdy_i)
+	 seqnum_reg <= seqnum;
    
    always @(posedge clk)
      if(reset | clear)
@@ -68,6 +81,7 @@ module vita_tx_deframer
 	  vita_state 		<= VITA_HEADER;
 	  {has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg, has_trailer_reg, is_sob_reg, is_eob_reg} 
 	    <= 0;
+	  seqnum_err <= 0;
        end
      else 
        if((vita_state == VITA_STORE) & fifo_space)
@@ -99,6 +113,7 @@ module vita_tx_deframer
 		  vita_state <= VITA_TICS;
 		else
 		  vita_state <= VITA_PAYLOAD;
+		seqnum_err <= ~(seqnum == next_seqnum);
 	     end // case: VITA_HEADER
 	   VITA_STREAMID :
 	     if(has_classid_reg)
@@ -145,7 +160,7 @@ module vita_tx_deframer
 
    assign line_done = (vector_phase == numchan);
    
-   wire [4+64+32*MAXCHAN-1:0] fifo_i;
+   wire [FIFOWIDTH-1:0] fifo_i;
    reg [63:0] 		      send_time;
    reg [31:0] 		      sample_a, sample_b, sample_c, sample_d;
    
@@ -169,13 +184,14 @@ module vita_tx_deframer
        endcase // case (vector_phase)
    
    wire 		      store = (vita_state == VITA_STORE);
-   fifo_short #(.WIDTH(4+64+32*MAXCHAN)) short_tx_q
+   fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q
      (.clk(clk), .reset(reset), .clear(clear),
       .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space),
       .dataout(sample_fifo_o), .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i) );
 
    // sob, eob, has_secs (send_at) ignored on all lines except first
-   assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time};
+   assign fifo_i = {sample_d,sample_c,sample_b,sample_a,seqnum_err,has_secs_reg,is_sob_reg,is_eob_reg,eop,
+		    12'd0,seqnum_reg,send_time};
 
    assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ;