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authorMatt Ettus <matt@ettus.com>2010-05-27 16:38:01 -0700
committerMatt Ettus <matt@ettus.com>2010-05-27 16:38:01 -0700
commitf1e7a07ff6843a0b1d41afb11a7895183329a436 (patch)
tree412416f78f48351a4d43bc7aa400b13f06b8d510 /usrp2/vrt/vita_tx_deframer.v
parentd87035457d623fde5b141068f83bb891b7d6978e (diff)
parentb38d2424b1ac3242146fc9305d9e4ae80e21dede (diff)
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Merge branch 'udp' into u1e_merge_with_udp
* udp: better test program for just the tx side fix typo, no functionality difference ignores move dsp settings regs to reclocked setting bus. Works, gets us to within 18ps of passing timing reverting logic clean up which should have made timing better, but made it worse instead Conflicts: usrp2/control_lib/settings_bus.v usrp2/top/u2_core/u2_core.v
Diffstat (limited to 'usrp2/vrt/vita_tx_deframer.v')
-rw-r--r--usrp2/vrt/vita_tx_deframer.v2
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index 49428ead5..220d3b061 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -28,7 +28,7 @@ module vita_tx_deframer
reg [3:0] vita_state;
wire has_streamid, has_classid, has_secs, has_tics, has_trailer;
- assign has_streamid = (data_i[31:28]==4'b001);
+ assign has_streamid = (data_i[31:28]==4'b0001);
assign has_classid = data_i[27];
assign has_secs = ~(data_i[23:22]==2'b00);
assign has_tics = ~(data_i[21:20]==2'b00);