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| author | Matt Ettus <matt@ettus.com> | 2011-03-16 16:42:51 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-16 16:42:51 -0700 |
| commit | b357b627fb3f519408ca38ebadc9f4ae6d57de80 (patch) | |
| tree | d7f11bc309111c65f0e705e2e39f70a44101b941 /usrp2/vrt/vita_tx_control.v | |
| parent | 74979af6a089c67ac6579cb08040aec305032018 (diff) | |
| download | uhd-b357b627fb3f519408ca38ebadc9f4ae6d57de80.tar.gz uhd-b357b627fb3f519408ca38ebadc9f4ae6d57de80.tar.bz2 uhd-b357b627fb3f519408ca38ebadc9f4ae6d57de80.zip | |
clean up a bunch of warnings and incorrect bus widths
Diffstat (limited to 'usrp2/vrt/vita_tx_control.v')
| -rw-r--r-- | usrp2/vrt/vita_tx_control.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index e966d987c..14b97a215 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -71,7 +71,7 @@ module vita_tx_control wire [31:0] error_policy; setting_reg #(.my_addr(BASE+3)) sr_error_policy - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(error_policy),.changed()); wire policy_wait = error_policy[0]; |