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author | Matt Ettus <matt@ettus.com> | 2010-10-08 14:01:33 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2010-10-08 14:01:33 -0700 |
commit | 37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03 (patch) | |
tree | 0662e958984222a8203de1b2fdea372d649525b4 /usrp2/vrt/vita_tx_control.v | |
parent | 26ada69153c8db487dda81ca63a5ea9c7ac6ba88 (diff) | |
download | uhd-37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03.tar.gz uhd-37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03.tar.bz2 uhd-37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03.zip |
checkpoint in flow control packet generation
Diffstat (limited to 'usrp2/vrt/vita_tx_control.v')
-rw-r--r-- | usrp2/vrt/vita_tx_control.v | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v index d0516bec8..61cd9edb5 100644 --- a/usrp2/vrt/vita_tx_control.v +++ b/usrp2/vrt/vita_tx_control.v @@ -8,7 +8,8 @@ module vita_tx_control input [63:0] vita_time, output error, output reg [31:0] error_code, - + output reg packet_consumed, + // From vita_tx_deframer input [5+64+16+WIDTH-1:0] sample_fifo_i, input sample_fifo_src_rdy_i, @@ -154,9 +155,14 @@ module vita_tx_control assign sample_fifo_dst_rdy_o = (ibs_state == IBS_ERROR) | (strobe & (ibs_state == IBS_RUN)); // FIXME also cleanout assign run = (ibs_state == IBS_RUN) | (ibs_state == IBS_CONT_BURST); - //assign error = (ibs_state == IBS_ERROR_DONE); assign error = send_error; + always @(posedge clk) + if(reset) + packet_consumed <= 0; + else + packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o; + assign debug = { { now,early,late,too_early,eop,eob,sob,send_at }, { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] }, { 8'b0 }, |