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authorMatt Ettus <matt@ettus.com>2010-07-16 16:17:35 -0700
committerMatt Ettus <matt@ettus.com>2010-07-28 10:00:43 -0700
commitbbbf8778b2924b6e285529d6547bcf471092510a (patch)
tree073559af0aa4eb33458aacc439b40812fca48b1c /usrp2/vrt/vita_tx_chain.v
parent33083078546a910268ee404fc592c7df31451ebc (diff)
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checkpoint. New context packet generator to report underruns and other errors
Diffstat (limited to 'usrp2/vrt/vita_tx_chain.v')
-rw-r--r--usrp2/vrt/vita_tx_chain.v43
1 files changed, 43 insertions, 0 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
new file mode 100644
index 000000000..17cfe1799
--- /dev/null
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -0,0 +1,43 @@
+
+module vita_tx_chain
+ #(parameter SR_TX_CTRL=0,
+ parameter SR_TX_DSP=0)
+ (input dsp_clk, input dsp_rst,
+ input set_stb_dsp, input [7:0] set_addr_dsp, input [31:0] set_data_dsp,
+ input [63:0] vita_time,
+ input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
+ output [15:0] dac_a, output [15:0] dac_b,
+ output underrun, output run_tx,
+ output [31:0] debug);
+
+ wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp;
+ wire [99:0] tx1_data;
+ wire tx1_src_rdy, tx1_dst_rdy;
+ wire clear_vita;
+ wire [31:0] sample_tx;
+
+ vita_tx_deframer #(.BASE(SR_TX_CTRL), .MAXCHAN(1)) vita_tx_deframer
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o),
+ .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy),
+ .debug(debug_vtd) );
+
+ vita_tx_control #(.BASE(SR_TX_CTRL), .WIDTH(32)) vita_tx_control
+ (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_vita),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .vita_time(vita_time),.underrun(underrun),
+ .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .debug(debug_vtc) );
+
+ dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
+ (.clk(dsp_clk),.rst(dsp_rst),
+ .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
+ .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+ .dac_a(dac_a),.dac_b(dac_b),
+ .debug(debug_tx_dsp) );
+
+ assign debug = debug_vtc | debug_vtd;
+
+endmodule // vita_tx_chain