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| author | Matt Ettus <matt@ettus.com> | 2010-10-08 14:01:33 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-10-08 14:01:33 -0700 |
| commit | 37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03 (patch) | |
| tree | 0662e958984222a8203de1b2fdea372d649525b4 /usrp2/vrt/vita_tx_chain.v | |
| parent | 26ada69153c8db487dda81ca63a5ea9c7ac6ba88 (diff) | |
| download | uhd-37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03.tar.gz uhd-37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03.tar.bz2 uhd-37f928fa5a3c01bd522a1d0db17d88ce4cdd0e03.zip | |
checkpoint in flow control packet generation
Diffstat (limited to 'usrp2/vrt/vita_tx_chain.v')
| -rw-r--r-- | usrp2/vrt/vita_tx_chain.v | 28 |
1 files changed, 19 insertions, 9 deletions
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v index 662cdca62..12e94b1a8 100644 --- a/usrp2/vrt/vita_tx_chain.v +++ b/usrp2/vrt/vita_tx_chain.v @@ -24,9 +24,10 @@ module vita_tx_chain wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire error; + wire error, packet_consumed; wire [31:0] error_code; wire clear_seqnum; + wire [15:0] current_seqnum; assign underrun = error; assign message = error_code; @@ -40,6 +41,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .data_i(tx_data_i), .src_rdy_i(tx_src_rdy_i), .dst_rdy_o(tx_dst_rdy_o), .sample_fifo_o(tx1_data), .sample_fifo_src_rdy_o(tx1_src_rdy), .sample_fifo_dst_rdy_i(tx1_dst_rdy), + .current_seqnum(current_seqnum), .debug(debug_vtd) ); vita_tx_control #(.BASE(BASE_CTRL), .WIDTH(32*MAXCHAN)) vita_tx_control @@ -47,7 +49,7 @@ module vita_tx_chain .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time),.error(error),.error_code(error_code), .sample_fifo_i(tx1_data), .sample_fifo_src_rdy_i(tx1_src_rdy), .sample_fifo_dst_rdy_o(tx1_dst_rdy), - .sample(sample_tx), .run(run), .strobe(strobe_tx), + .sample(sample_tx), .run(run), .strobe(strobe_tx), .packet_consumed(packet_consumed), .debug(debug_vtc) ); dsp_core_tx #(.BASE(BASE_DSP)) dsp_core_tx @@ -59,13 +61,21 @@ module vita_tx_chain generate if(REPORT_ERROR==1) - gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt - (.clk(clk), .reset(reset), .clear(clear_vita), - .trigger(error), .sent(), - .streamid(streamid), .vita_time(vita_time), .message(message), - .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + begin + gen_context_pkt #(.PROT_ENG_FLAGS(PROT_ENG_FLAGS)) gen_tx_err_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .trigger(trigger),.error(error), .sent(), + .streamid(streamid), .vita_time(vita_time), .message(message), + .seqnum0(current_seqnum), .seqnum1(16'd0), + .data_o(err_data_o), .src_rdy_o(err_src_rdy_o), .dst_rdy_i(err_dst_rdy_i)); + trigger_context_pkt #(.BASE(BASE_CTRL)) trigger_context_pkt + (.clk(clk), .reset(reset), .clear(clear_vita), + .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), + .packet_consumed(packet_consumed), .trigger(trigger)); + end endgenerate - - assign debug = debug_vtc | debug_vtd; + + //assign debug = debug_vtc | debug_vtd; + assign debug = { debug_vtd[15:0], current_seqnum }; endmodule // vita_tx_chain |