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| author | Matt Ettus <matt@ettus.com> | 2010-07-19 15:26:28 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-07-19 15:26:28 -0700 |
| commit | 8e9d08ea7aece54fca7ba6c4898614891440ab71 (patch) | |
| tree | 90f19252d0d1dc372469f044f70b41132499b867 /usrp2/vrt/vita_rx_control.v | |
| parent | ed11f715c45ad129600e20849254e3899407002a (diff) | |
| parent | 33083078546a910268ee404fc592c7df31451ebc (diff) | |
| download | uhd-8e9d08ea7aece54fca7ba6c4898614891440ab71.tar.gz uhd-8e9d08ea7aece54fca7ba6c4898614891440ab71.tar.bz2 uhd-8e9d08ea7aece54fca7ba6c4898614891440ab71.zip | |
Merge branch 'ise12' into u2p
* ise12:
move declaration ahead of use
put run_tx and run_rx on the displayed LEDs
remove warnings
add mux and demux to build
mux multiple fifo streams into one. Allows priority or round robin
split fifo into 2 streams based on first line in each packet
fix to stop endless error packets
updated tests to match new features
error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
reload bit for vita rx ctrl
Diffstat (limited to 'usrp2/vrt/vita_rx_control.v')
| -rw-r--r-- | usrp2/vrt/vita_rx_control.v | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v index 669b8299d..93673d292 100644 --- a/usrp2/vrt/vita_rx_control.v +++ b/usrp2/vrt/vita_rx_control.v @@ -31,13 +31,13 @@ module vita_rx_control wire [63:0] rcvtime_pre; reg [63:0] rcvtime; - wire [29:0] numlines_pre; - wire send_imm_pre, chain_pre; - reg send_imm, chain; + wire [28:0] numlines_pre; + wire send_imm_pre, chain_pre, reload_pre; + reg send_imm, chain, reload; wire full_ctrl, read_ctrl, empty_ctrl, write_ctrl; reg sc_pre2; wire [33:0] fifo_line; - reg [29:0] lines_left; + reg [28:0] lines_left, lines_total; reg [2:0] ibs_state; wire now, early, late; wire sample_fifo_in_rdy; @@ -67,7 +67,7 @@ module vita_rx_control shortfifo #(.WIDTH(96)) commandfifo (.clk(clk),.rst(reset),.clear(clear_int), .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl), - .dataout({send_imm_pre,chain_pre,numlines_pre,rcvtime_pre}), + .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}), .read(read_ctrl), .empty(empty_ctrl), .occupied(command_queue_len), .space() ); @@ -111,9 +111,11 @@ module vita_rx_control begin ibs_state <= IBS_IDLE; lines_left <= 0; + lines_total <= 0; rcvtime <= 0; send_imm <= 0; chain <= 0; + reload <= 0; end else case(ibs_state) @@ -121,10 +123,12 @@ module vita_rx_control if(~empty_ctrl) begin lines_left <= numlines_pre; + lines_total <= numlines_pre; rcvtime <= rcvtime_pre; ibs_state <= IBS_WAITING; send_imm <= send_imm_pre; chain <= chain_pre; + reload <= reload_pre; end IBS_WAITING : if(go_now) @@ -141,14 +145,21 @@ module vita_rx_control if(lines_left == 1) if(~chain) ibs_state <= IBS_IDLE; + else if(empty_ctrl & reload) + begin + ibs_state <= IBS_RUNNING; + lines_left <= lines_total; + end else if(empty_ctrl) ibs_state <= IBS_BROKENCHAIN; else begin lines_left <= numlines_pre; + lines_total <= numlines_pre; rcvtime <= rcvtime_pre; send_imm <= send_imm_pre; chain <= chain_pre; + reload <= reload_pre; if(numlines_pre == 0) // If we are told to stop here ibs_state <= IBS_IDLE; else |