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author | Josh Blum <josh@joshknows.com> | 2012-02-01 18:02:10 -0800 |
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committer | Josh Blum <josh@joshknows.com> | 2012-02-01 18:02:10 -0800 |
commit | 7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f (patch) | |
tree | 31bf389f0a241d4309bb042450dad4be81f39b3c /usrp2/vrt/vita_rx_chain.v | |
parent | 6bbcb202183c5a0ab5351a0c052981408e4719cb (diff) | |
download | uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.tar.gz uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.tar.bz2 uhd-7e6a08556b01fcb6ad113c2ff0db4abe5aeac38f.zip |
dsp rework: custom engine module for rx/tx vita chain
Diffstat (limited to 'usrp2/vrt/vita_rx_chain.v')
-rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index 150da31c9..bd416f563 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -20,9 +20,11 @@ module vita_rx_chain #(parameter BASE=0, parameter UNIT=0, parameter FIFOSIZE=10, - parameter PROT_ENG_FLAGS=1) + parameter PROT_ENG_FLAGS=1, + parameter DSP_NUMBER=0) (input clk, input reset, input set_stb, input [7:0] set_addr, input [31:0] set_data, + input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user, input [63:0] vita_time, input [31:0] sample, input strobe, output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i, @@ -72,9 +74,10 @@ module vita_rx_chain .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2)); - dspengine_16to8 #(.BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_16to8 - (.clk(clk),.reset(reset),.clear(clear), - .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), + custom_engine_rx #(.DSPNO(DSP_NUMBER), .MAIN_SETTINGS_BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_rx + (.clock(clk),.reset(reset),.clear(clear), + .set_stb_main(set_stb), .set_addr_main(set_addr), .set_data_main(set_data), + .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), .access_skip_read(access_skip_read), .access_adr(access_adr), .access_len(access_len), .access_dat_i(buf_to_dsp), .access_dat_o(dsp_to_buf)); |