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| author | Matt Ettus <matt@ettus.com> | 2011-03-05 23:28:54 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-05 23:28:54 -0800 |
| commit | 8a49d85f0b26a0ab459d41831dc2b03c91744458 (patch) | |
| tree | 95b6686d273102858c47efbb3b569daa14feac7e /usrp2/vrt/vita_rx_chain.v | |
| parent | 354b55e52ed4edd4f417e7cb28b93960bebaf762 (diff) | |
| download | uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.tar.gz uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.tar.bz2 uhd-8a49d85f0b26a0ab459d41831dc2b03c91744458.zip | |
u2/u2p: moved dsp framer into vita_rx_chain
Diffstat (limited to 'usrp2/vrt/vita_rx_chain.v')
| -rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index f5578eb15..2410dcc37 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -1,6 +1,8 @@ module vita_rx_chain - #(parameter BASE=0) + #(parameter BASE=0, + parameter UNIT=0, + parameter FIFOSIZE=10) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, output overrun, @@ -9,8 +11,8 @@ module vita_rx_chain output [31:0] debug ); wire [100:0] sample_data; - wire sample_dst_rdy, sample_src_rdy; - wire [31:0] vrc_debug, vrf_debug; + wire sample_dst_rdy, sample_src_rdy; + wire [31:0] vrc_debug, vrf_debug; vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), @@ -24,10 +26,14 @@ module vita_rx_chain (.clk(clk), .reset(reset), .clear(clear), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .sample_fifo_i(sample_data), .sample_fifo_dst_rdy_o(sample_dst_rdy), .sample_fifo_src_rdy_i(sample_src_rdy), - .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i), - .fifo_occupied(), .fifo_full(), .fifo_empty(), + .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .debug_rx(vrf_debug) ); + dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36 + (.clk(clk), .reset(reset), .clear(clear), + .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), + .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); + assign debug = vrc_debug; // | vrf_debug; endmodule // vita_rx_chain |