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| author | Matt Ettus <matt@ettus.com> | 2010-03-25 21:00:25 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-03-25 21:00:25 -0700 |
| commit | f979a9d4e7b9664e046aaca54357e46782c4aa51 (patch) | |
| tree | d48bb446844d647977c2ba4d52fcb64d935df079 /usrp2/vrt/vita_rx.build | |
| parent | b74388567c0ed3048e45158ac077e31def59fea1 (diff) | |
| parent | 16818dc98e97b69a028c47e66ebfb16e32565533 (diff) | |
| download | uhd-f979a9d4e7b9664e046aaca54357e46782c4aa51.tar.gz uhd-f979a9d4e7b9664e046aaca54357e46782c4aa51.tar.bz2 uhd-f979a9d4e7b9664e046aaca54357e46782c4aa51.zip | |
Merge branch 'udp' into u1e
Diffstat (limited to 'usrp2/vrt/vita_rx.build')
| -rwxr-xr-x | usrp2/vrt/vita_rx.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build new file mode 100755 index 000000000..f6d2d75a3 --- /dev/null +++ b/usrp2/vrt/vita_rx.build @@ -0,0 +1 @@ +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v |