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| author | Nick Foster <nick@nerdnetworks.org> | 2010-07-19 18:13:56 -0700 |
|---|---|---|
| committer | Nick Foster <nick@nerdnetworks.org> | 2010-07-19 18:13:56 -0700 |
| commit | 3d96ee15d99bf08554a3075b5814dabc51eef389 (patch) | |
| tree | 1cc93e3a29827a10bb7562cf45fb9d7cd297956f /usrp2/vrt/vita_rx.build | |
| parent | 219934cb7ab33356c7c53409a9c16da6097135dc (diff) | |
| parent | 814b06dff3ffccdf7d8f80fcb93d21d740612804 (diff) | |
| download | uhd-3d96ee15d99bf08554a3075b5814dabc51eef389.tar.gz uhd-3d96ee15d99bf08554a3075b5814dabc51eef389.tar.bz2 uhd-3d96ee15d99bf08554a3075b5814dabc51eef389.zip | |
Merge branch 'u2p' of ettus.sourcerepo.com:ettus/fpgapriv into u2p
Diffstat (limited to 'usrp2/vrt/vita_rx.build')
| -rwxr-xr-x | usrp2/vrt/vita_rx.build | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build index f6d2d75a3..010d1be6e 100755 --- a/usrp2/vrt/vita_rx.build +++ b/usrp2/vrt/vita_rx.build @@ -1 +1 @@ -iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v +iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v |